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vga framebuffer: use 640x480@60Hz video timings

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- we still can only display 400 lines, so 80 blank lines
  are added at the bottom
- we get square pixels this way and are hopefully more
  compatible with monitors and other devices like
  scan converters and capture cards
This commit is contained in:
slederer 2025-06-22 00:33:02 +02:00
parent e08d610aef
commit ecff04a7a0
2 changed files with 39 additions and 18 deletions
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27
tridoracpu/tridoracpu.srcs/vgafb.v
View file

@ -6,8 +6,11 @@
// Learn more at https://projectf.io // Learn more at https://projectf.io
//128K video memory is not enough for 640x480x4 //128K video memory is not enough for 640x480x4
`define RES_640_400 //`define RES_640_400
//`define RES_1024_768 //`define RES_1024_768
// RES_640_480 mode displays 400 lines with 640x480/60 video timings,
// adding blank lines at the bottom
`define RES_640_480
module display_timings #( module display_timings #(
H_RES=640, // horizontal resolution (pixels) H_RES=640, // horizontal resolution (pixels)
@ -126,6 +129,8 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
localparam COLOR_WIDTH = 12; localparam COLOR_WIDTH = 12;
localparam PALETTE_WIDTH = 4; localparam PALETTE_WIDTH = 4;
localparam signed PIC_LINES = 400; // visible picture lines
// Display Clocks // Display Clocks
wire pix_clk = CLK; // pixel clock wire pix_clk = CLK; // pixel clock
wire clk_lock = 1; // clock locked? wire clk_lock = 1; // clock locked?
@ -202,6 +207,18 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
.V_BP(35), .V_BP(35),
.H_POL(0), .H_POL(0),
.V_POL(1) .V_POL(1)
`endif
`ifdef RES_640_480
.H_RES(640), // 640 800 1280 1920
.V_RES(480), // 480 600 720 1080
.H_FP(16), // 16 40 110 88
.H_SYNC(96), // 96 128 40 44
.H_BP(48), // 48 88 220 148
.V_FP(10), // 10 1 5 4
.V_SYNC(2), // 2 4 5 5
.V_BP(33), // 33 23 20 36
.H_POL(0), // 0 1 1 1
.V_POL(0) // 0 1 1 1
`endif `endif
) )
display_timings_inst ( display_timings_inst (
@ -217,6 +234,8 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
.o_sy(sy) .o_sy(sy)
); );
wire pic_enable = (sy >= 0) && (sy < PIC_LINES); // when to display pixels from VRAM
wire [7:0] red; wire [7:0] red;
wire [7:0] green; wire [7:0] green;
wire [7:0] blue; wire [7:0] blue;
@ -288,7 +307,7 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
// 12 bit RGB palette // 12 bit RGB palette
assign VGA_HS = h_sync; assign VGA_HS = h_sync;
assign VGA_VS = v_sync; assign VGA_VS = v_sync;
assign VGA_R = de ? color_data[11:8] : 4'b0; assign VGA_R = (pic_enable && de) ? color_data[11:8] : 4'b0;
assign VGA_G = de ? color_data[7:4] : 4'b0; assign VGA_G = (pic_enable && de) ? color_data[7:4] : 4'b0;
assign VGA_B = de ? color_data[3:0] : 4'b0; assign VGA_B = (pic_enable && de) ? color_data[3:0] : 4'b0;
endmodule endmodule

30
tridoracpu/tridoracpu.xpr
View file

@ -351,7 +351,9 @@
<Runs Version="1" Minor="22"> <Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -361,9 +363,7 @@
</Run> </Run>
<Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true"> <Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -371,21 +371,25 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Increase placer effort in the post-placement optimization phase, and disable timing relaxation in the router." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Best predicted directive for place_design." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Performance_RefinePlacement" Flow="Vivado Implementation 2020"/> <StratHandle Name="Performance_Auto_1" Flow="Vivado Implementation 2024">
<Desc>Best predicted directive for place_design.</Desc>
</StratHandle>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design">
<Option Id="Directive">0</Option>
</Step>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>
<Step Id="place_design"> <Step Id="place_design">
<Option Id="Directive">7</Option> <Option Id="Directive">20</Option>
</Step> </Step>
<Step Id="post_place_power_opt_design"/> <Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"> <Step Id="phys_opt_design">
<Option Id="Directive">0</Option> <Option Id="Directive">2</Option>
</Step> </Step>
<Step Id="route_design"> <Step Id="route_design">
<Option Id="Directive">0</Option> <Option Id="Directive">1</Option>
</Step> </Step>
<Step Id="post_route_phys_opt_design"/> <Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"> <Step Id="write_bitstream">
@ -393,15 +397,13 @@
</Step> </Step>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true"> <Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design"/>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>