update documentation for October 2025 update

README.md

@@ -41,6 +41,25 @@ Other inspirations were, among others, in no particular order:
 - the Magic-1 by Bill Buzbee
 - the OPC by revaldinho
 
+## October 2025 Update
+This update introduces a data cache for the Tridora-CPU. It is similar to the instruction cache
+as it caches the 16 bytes coming from the DRAM memory controller. It is a write-back cache, i.e.
+when a word inside the cached area is written, it updates the cache instead of invalidating it.
+
+This is important because there are many idioms in the stack machine assembly language where you
+store a local variable and then read it again (e.g. updating a loop variable).
+
+Since for most programs, the user stack and parts of the heap are inside the DRAM area, the data cache
+has a more noticable impact. In the benchmark program that was already used for the last update,
+the data cache results in a 50% improvement for the empty loop test. This is in comparison to the version
+without data cache but with the instruction cache, both running code out of DRAM.
+
+It is also noticable for compile times: With the data cache, compiling and assembling the
+"hello,world" program takes 16 seconds instead of 20. With a little tweak of the SD-Card controller
+that slightly increased the data transfer rate, the build time goes down to 15 seconds.
+
+Also, an audio controller was added that allows interrupt-driven sample playback via an AMP2 PMOD.
+
 ## April 2025 Update
 The clock has been reduced to 77 MHz from 83 MHz. Apparently the design was at the limit and
 timing problems were cropping up seemingly at random. Reducing the clock speed made some
@@ -62,7 +81,7 @@ on the emulator image.
 - the [Hackaday project](https://hackaday.io/project/198324-tridora-cpu) (mostly copy-paste from this README)
 - the [YouTube channel](https://www.youtube.com/@tridoracpu/videos) with some demo videos
 - the [emulator](https://git.insignificance.de/slederer/-/packages/generic/tridoraemu/0.0.5/files/12) (source and windows binary)
-- the [FPGA bitstream](https://git.insignificance.de/slederer/-/packages/generic/tdr-bitstream/0.0.2/files/14) for the Arty-A7-35T board
+- the [FPGA bitstream](https://git.insignificance.de/slederer/-/packages/generic/tdr-bitstream/0.0.3/files/15) for the Arty-A7-35T board
 - an [SD-card image](https://git.insignificance.de/slederer/-/packages/generic/tdr-cardimage/0.0.4/files/13)
 
 Contact the author here: tridoracpu [at] insignificance.de

doc/mem.md

@@ -34,3 +34,4 @@ Currently, only I/O slots 0-3 are being used.
 | 1      | $880    | SPI-SD     |
 | 2      | $900    | VGA        |
 | 3      | $980    | IRQC       |
+| 4      | $A00    | TDRAUDIO   |