tdraudio: first step of implementing a sound generator

tridoracpu/tridoracpu.srcs/top.v

@@ -10,6 +10,7 @@
 //`define clock clk_1hz
 `define ENABLE_VGAFB
 `define ENABLE_MICROSD
+`define ENABLE_TDRAUDIO
 
 module top(
     input wire clk,
@@ -60,6 +61,13 @@ module top(
     output wire sd_sck,
     input wire  sd_cd
 `endif
+
+`ifdef ENABLE_TDRAUDIO
+    ,
+    output wire amp2_ain,
+    output wire amp2_gain,
+    output wire amp2_shutdown_n
+`endif
 );
 
     reg clk_1hz;
@@ -220,6 +228,7 @@ module top(
     assign uart_tx_data = mem_write_data[7:0];
     assign uart_rd_data = { {WIDTH-10{1'b1}}, uart_rx_avail, uart_tx_busy, uart_rx_data };
 
+    // interrupt controller
     reg timer_tick;
     reg[23:0] tick_count;
     wire [1:0] irq_in = { timer_tick, uart_rx_avail };
@@ -228,6 +237,25 @@ module top(
     wire irqc_seten = mem_write_data[7];
     wire irqc_cs = io_enable && (io_slot == 3);
 
+`ifdef ENABLE_TDRAUDIO
+    wire [WIDTH-1:0] tdraudio_wr_data;
+    wire [WIDTH-1:0] tdraudio_rd_data;
+    wire tdraudio_rd_en, tdraudio_wr_en;
+
+    wire tdraudio_cs_en = io_enable && (io_slot == 4);
+    assign tdraudio_rd_en = tdraudio_cs_en && mem_read_enable;
+    assign tdraudio_wr_en = tdraudio_cs_en && mem_write_enable;
+    assign tdraudio_wr_data = mem_write_data;
+
+    tdraudio tdraudio0(`clock, ~rst,
+        mem_addr[3:0],
+        tdraudio_rd_data,
+        tdraudio_wr_data,
+        tdraudio_rd_en,
+        tdraudio_wr_en,
+        amp2_ain, amp2_gain, amp2_shutdown_n);
+`endif
+
     assign io_rd_data = (io_slot == 0) ? uart_rd_data :
     `ifdef ENABLE_MICROSD
                         (io_slot == 1) ? spi_rd_data :
@@ -236,7 +264,9 @@ module top(
                         (io_slot == 2) ? fb_rd_data :
     `endif
                         (io_slot == 3) ? irqc_rd_data:
-
+    `ifdef ENABLE_TDRAUDIO
+                        (io_slot == 4) ? tdraudio_rd_data:
+    `endif
                         -1;
 
     buart #(.CLKFREQ(`clkfreq)) uart0(`clock, rst,