slederer/Tridora-CPU
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tridoracpu: cleaned up top a bit, removed some warnings

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slederer 2025-12-15 00:53:36 +01:00
parent 0016d4ea25
commit d2f3b09e72
5 changed files with 47 additions and 58 deletions
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21
tridoracpu/tridoracpu.srcs/top.v
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@ -15,9 +15,6 @@
module top(
input wire clk,
input wire rst,
input wire btn0,
input wire sw0,
input wire sw1,
output wire led0,
output wire led1,
output wire led2,
@ -229,6 +226,15 @@ module top(
assign uart_rd_data = { {WIDTH-10{1'b1}}, uart_rx_avail, uart_tx_busy, uart_rx_data };
wire audio_irq;
buart #(.CLKFREQ(`clkfreq)) uart0(`clock, rst,
uart_baud,
uart_txd_in, uart_rxd_out,
uart_rx_clear, uart_tx_en,
uart_rx_avail, uart_tx_busy,
uart_tx_data, uart_rx_data);
// audio controller
`ifdef ENABLE_TDRAUDIO
wire [WIDTH-1:0] tdraudio_wr_data;
wire [WIDTH-1:0] tdraudio_rd_data;
@ -273,13 +279,6 @@ module top(
`endif
-1;
buart #(.CLKFREQ(`clkfreq)) uart0(`clock, rst,
uart_baud,
uart_txd_in, uart_rxd_out,
uart_rx_clear, uart_tx_en,
uart_rx_avail, uart_tx_busy,
uart_tx_data, uart_rx_data);
// CPU -----------------------------------------------------------------
stackcpu cpu0(.clk(`clock), .rst(rst), .irq(irq),
.addr(mem_addr),
@ -287,7 +286,7 @@ module top(
.read_ins(dram_read_ins),
.data_out(mem_write_data), .write_enable(mem_write_enable),
.mem_wait(mem_wait),
.led1(led1), .led2(led2), .led3(led3));
.debug1(led1), .debug2(led2), .debug3(led3));
// Interrupt Controller
irqctrl irqctrl0(`clock, irq_in, irqc_cs, mem_write_enable,