tridoracpu: reduce clock speed, fix vblank flag in vgafb
This commit is contained in:
slederer
parent
4f504c0f48
commit
c2d7c6627a
7 changed files with 76 additions and 47 deletions
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@ -1,9 +1,10 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2020.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
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<!-- Product Version: Vivado v2024.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="49" Path="./tridoracpu.xpr">
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<Project Product="Vivado" Version="7" Minor="67" Path="C:/Users/sebastian/develop/Tridora-NexysA7/Tridora-CPU/tridoracpu/tridoracpu.xpr">
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@ -12,20 +13,37 @@
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@ -35,6 +53,8 @@
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@ -47,13 +67,13 @@
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@ -65,8 +85,10 @@
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@ -233,18 +255,6 @@
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@ -298,6 +308,18 @@
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@ -317,8 +339,8 @@
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@ -328,17 +350,17 @@
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@ -364,9 +386,9 @@
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@ -377,7 +399,7 @@
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