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tridoracpu: reduce clock speed, fix vblank flag in vgafb

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slederer 2025-03-13 22:37:56 +01:00
parent 4f504c0f48
commit c2d7c6627a
7 changed files with 76 additions and 47 deletions
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8
tridoracpu/tridoracpu.srcs/vgafb.v
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@ -62,10 +62,11 @@ module display_timings #(
// o_scanline: high for one tick at the start of each visible scanline
assign o_scanline = (o_sy >= VA_STA) && (o_sy <= VA_END) && (o_sx == H_STA);
// set vblank at end of frame, clear at start
always @(posedge i_pix_clk)
begin
if(o_frame) o_vblank <= 1;
else if (o_de) o_vblank <= 0;
if(o_sy == VA_END) o_vblank <= 1;
else if (o_sy == -1) o_vblank <= 0;
end
always @ (posedge i_pix_clk)
@ -175,6 +176,7 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
wire scanline; // scanline start
wire vblank; // vertical blank
reg vblank_buf; // vertical blank in cpu clock domain
reg vblank_xfer; // vertical blank clock domain crossing
display_timings #( // 640x480 800x600 1280x720 1920x1080
`ifdef RES_1024_768
@ -233,7 +235,7 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
always @(posedge pix_clk) frame_d <= frame;
always @(posedge cpu_clk) vblank_buf <= vblank;
always @(posedge cpu_clk) { vblank_buf, vblank_xfer } <= { vblank_xfer, vblank };
always @(posedge cpu_clk)
begin