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tridoracpu: first attempt at instruction cache

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slederer 2025-03-16 00:10:53 +01:00
parent 3f40c50170
commit b6bd487b7e
5 changed files with 75 additions and 62 deletions
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1
.gitignore vendored
View file

@ -33,6 +33,7 @@ pcomp/sdis
tridoraemu/tridoraemu tridoraemu/tridoraemu
**/tridoracpu.cache/ **/tridoracpu.cache/
**/tridoracpu.hw/ **/tridoracpu.hw/
**/tridoracpu.gen/
**/tridoracpu.ip_user_files/ **/tridoracpu.ip_user_files/
**/tridoracpu.runs/ **/tridoracpu.runs/
*.log *.log

45
tridoracpu/tridoracpu.srcs/dram_bridge.v
View file

@ -8,6 +8,7 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
input wire [WIDTH-1:0] mem_write_data, input wire [WIDTH-1:0] mem_write_data,
input wire mem_read_enable, input wire mem_read_enable,
input wire mem_write_enable, input wire mem_write_enable,
input wire mem_read_ins,
output wire mem_wait, output wire mem_wait,
input wire rst_n, input wire rst_n,
@ -105,31 +106,35 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
.sys_rst (rst_n) .sys_rst (rst_n)
); );
// reg [DRAM_DATA_WIDTH-1:0] read_cache; reg [DRAM_DATA_WIDTH-1:0] ins_cache;
// reg [ADDR_WIDTH-1:0] cached_addr; reg [DRAM_ADDR_WIDTH-1:4] cached_addr;
// wire cache_hit = cached_addr == mem_addr; wire cache_hit = mem_read_ins && (cached_addr == mem_addr[DRAM_ADDR_WIDTH:4]);
// wire [DRAM_DATA_WIDTH-1:0] read_data_wrapper = cache_hit ? read_cache : app_rd_data; wire [DRAM_DATA_WIDTH-1:0] read_data_wrapper = cache_hit ? ins_cache : app_rd_data;
reg [WIDTH-1:0] read_buf; reg [WIDTH-1:0] read_buf;
reg read_inprogress = 0; reg read_inprogress = 0;
wire dram_read_enable = mem_read_enable && !cache_hit;
assign app_rd_data_end = 1'b1; assign app_rd_data_end = 1'b1;
//assign app_wdf_mask = 16'b1111111111111100;
// addresses on the memory interface are aligned to 16 bytes // addresses on the memory interface are aligned to 16 bytes
// and 28 bits wide (=256MB) // and 28 bits wide (=256MB)
assign app_addr = { mem_addr[DRAM_ADDR_WIDTH:4], 4'b0000 }; assign app_addr = { mem_addr[DRAM_ADDR_WIDTH:4], 4'b0000 };
//assign app_addr = { 28'b0 };
// select a word from the 128 bits transferred by the dram controller // select a word from the 128 bits transferred by the dram controller
// according to the lower bits of the address (ignoring bits 1:0) // according to the lower bits of the address (ignoring bits 1:0)
wire [WIDTH-1:0] read_word; wire [WIDTH-1:0] read_word;
wire [1:0] word_sel = mem_addr[3:2]; wire [1:0] word_sel = mem_addr[3:2];
assign read_word = word_sel == 3'b11 ? app_rd_data[31:0] : // assign read_word = word_sel == 3'b11 ? app_rd_data[31:0] :
word_sel == 3'b10 ? app_rd_data[63:32] : // word_sel == 3'b10 ? app_rd_data[63:32] :
word_sel == 3'b01 ? app_rd_data[95:64] : // word_sel == 3'b01 ? app_rd_data[95:64] :
app_rd_data[127:96]; // app_rd_data[127:96];
assign read_word = word_sel == 3'b11 ? read_data_wrapper[31:0] :
word_sel == 3'b10 ? read_data_wrapper[63:32] :
word_sel == 3'b01 ? read_data_wrapper[95:64] :
read_data_wrapper[127:96];
assign mem_read_data = app_rd_data_valid ? read_word : read_buf; assign mem_read_data = app_rd_data_valid ? read_word : read_buf;
@ -145,21 +150,31 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
assign app_wdf_end = mem_write_enable & write_ready; assign app_wdf_end = mem_write_enable & write_ready;
assign app_wdf_data = { {4{mem_write_data}} }; assign app_wdf_data = { {4{mem_write_data}} };
assign mem_wait = (mem_read_enable & ~read_inprogress) | assign mem_wait = (dram_read_enable & ~read_inprogress) |
(mem_write_enable & (~app_wdf_rdy | ~app_rdy)) | (mem_write_enable & (~app_wdf_rdy | ~app_rdy)) |
(read_inprogress & ~app_rd_data_valid); (read_inprogress & ~app_rd_data_valid);
assign app_en = (mem_read_enable & ~read_inprogress) | assign app_en = (dram_read_enable & ~read_inprogress) |
(mem_write_enable & write_ready); (mem_write_enable & write_ready);
assign app_cmd = mem_read_enable ? CMD_READ : CMD_WRITE; assign app_cmd = dram_read_enable ? CMD_READ : CMD_WRITE;
always @(posedge dram_front_clk) always @(posedge dram_front_clk)
begin begin
if(mem_read_enable & ~read_inprogress & app_rdy) if(mem_read_enable && mem_read_ins && ~cache_hit && app_rd_data_valid)
begin
ins_cache <= mem_read_data;
cached_addr <= mem_addr[DRAM_ADDR_WIDTH:4];
end
end
always @(posedge dram_front_clk)
begin
if(dram_read_enable & ~read_inprogress & app_rdy)
read_inprogress <= 1; read_inprogress <= 1;
if(read_inprogress & app_rd_data_valid) if(read_inprogress & app_rd_data_valid)
read_inprogress <= 0; read_inprogress <= 0;
if(mem_read_enable & app_rd_data_valid) if(dram_read_enable & app_rd_data_valid)
read_buf <= mem_read_data; read_buf <= mem_read_data;
end end
endmodule endmodule

12
tridoracpu/tridoracpu.srcs/stackcpu.v
View file

@ -11,20 +11,14 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
output reg [ADDR_WIDTH-1:0] addr, output reg [ADDR_WIDTH-1:0] addr,
input wire [WIDTH-1:0] data_in, input wire [WIDTH-1:0] data_in,
output wire read_enable, output wire read_enable,
output wire read_ins,
output wire [WIDTH-1:0] data_out, output wire [WIDTH-1:0] data_out,
output wire write_enable, output wire write_enable,
input wire mem_wait, input wire mem_wait,
output wire led1, output wire led1,
output wire led2, output wire led2,
output wire led3, output wire led3
output wire [WIDTH-1:0] debug_out1,
output wire [WIDTH-1:0] debug_out2,
output wire [WIDTH-1:0] debug_out3,
output wire [WIDTH-1:0] debug_out4,
output wire [WIDTH-1:0] debug_out5,
output wire [WIDTH-1:0] debug_out6
); );
localparam EVAL_STACK_INDEX_WIDTH = 6; localparam EVAL_STACK_INDEX_WIDTH = 6;
@ -182,6 +176,8 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
assign mem_read_enable = (seq_state == FETCH) || (seq_state == EXEC && mem_read); assign mem_read_enable = (seq_state == FETCH) || (seq_state == EXEC && mem_read);
assign mem_write_enable = (seq_state == MEM && mem_write); assign mem_write_enable = (seq_state == MEM && mem_write);
assign read_ins = (seq_state == FETCH) || (seq_state == DECODE);
initial initial
begin begin
PC <= 0; nPC <= 0; seq_state <= MEM; PC <= 0; nPC <= 0; seq_state <= MEM;

22
tridoracpu/tridoracpu.srcs/top.v
View file

@ -72,6 +72,7 @@ module top(
wire [WIDTH-1:0] mem_read_data; wire [WIDTH-1:0] mem_read_data;
wire [WIDTH-1:0] mem_write_data; wire [WIDTH-1:0] mem_write_data;
(* KEEP *) wire mem_wait; (* KEEP *) wire mem_wait;
assign led0 = mem_wait;
(* KEEP *) wire mem_read_enable; (* KEEP *) wire mem_read_enable;
(* KEEP *) wire mem_write_enable; (* KEEP *) wire mem_write_enable;
@ -81,14 +82,6 @@ module top(
wire irq; wire irq;
// assign led0 = mem_wait;
wire [WIDTH-1:0] debug_data1, debug_data2,
debug_data3, debug_data4,
debug_data5, debug_data6;
assign led0 = debug_data6[0];
wire cpuclk, cpuclk_locked; wire cpuclk, cpuclk_locked;
wire dram_refclk200; wire dram_refclk200;
wire pixclk; wire pixclk;
@ -98,9 +91,11 @@ module top(
wire [ADDR_WIDTH-1:0] dram_addr; wire [ADDR_WIDTH-1:0] dram_addr;
wire [WIDTH-1:0] dram_read_data, dram_write_data; wire [WIDTH-1:0] dram_read_data, dram_write_data;
wire dram_read_enable, dram_write_enable, dram_wait; wire dram_read_enable, dram_write_enable, dram_wait;
wire dram_read_ins;
dram_bridge dram_bridge0 (dram_addr, dram_bridge dram_bridge0 (dram_addr,
dram_read_data, dram_write_data, dram_read_enable, dram_write_enable, dram_wait, dram_read_data, dram_write_data, dram_read_enable, dram_write_enable,
dram_read_ins, dram_wait,
rst, cpuclk, dram_refclk200, rst, cpuclk, dram_refclk200,
ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr, ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr,
ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n,
@ -255,15 +250,10 @@ module top(
stackcpu cpu0(.clk(`clock), .rst(rst), .irq(irq), stackcpu cpu0(.clk(`clock), .rst(rst), .irq(irq),
.addr(mem_addr), .addr(mem_addr),
.data_in(mem_read_data), .read_enable(mem_read_enable), .data_in(mem_read_data), .read_enable(mem_read_enable),
.read_ins(dram_read_ins),
.data_out(mem_write_data), .write_enable(mem_write_enable), .data_out(mem_write_data), .write_enable(mem_write_enable),
.mem_wait(mem_wait), .mem_wait(mem_wait),
.led1(led1), .led2(led2), .led3(led3), .led1(led1), .led2(led2), .led3(led3));
.debug_out1(debug_data1),
.debug_out2(debug_data2),
.debug_out3(debug_data3),
.debug_out4(debug_data4),
.debug_out5(debug_data5),
.debug_out6(debug_data6));
// Interrupt Controller // Interrupt Controller
irqctrl irqctrl0(`clock, irq_in, irqc_cs, mem_write_enable, irqctrl irqctrl0(`clock, irq_in, irqc_cs, mem_write_enable,

57
tridoracpu/tridoracpu.xpr
View file

@ -1,10 +1,10 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2024.1 (64-bit) --> <!-- Product Version: Vivado v2024.2.2 (64-bit) -->
<!-- --> <!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. --> <!-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="67" Path="C:/Users/sebastian/develop/Tridora-NexysA7/Tridora-CPU/tridoracpu/tridoracpu.xpr"> <Project Product="Vivado" Version="7" Minor="68" Path="C:/Users/sebastian/develop/Tridora-NexysA7/Tridora-CPU/tridoracpu/tridoracpu.xpr">
<DefaultLaunch Dir="$PRUNDIR"/> <DefaultLaunch Dir="$PRUNDIR"/>
<Configuration> <Configuration>
<Option Name="Id" Val="ab60beb5e7ec4efc9a7b17699b9c3b13"/> <Option Name="Id" Val="ab60beb5e7ec4efc9a7b17699b9c3b13"/>
@ -29,13 +29,13 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/> <Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/> <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/> <Option Name="SimulatorVersionXsim" Val="2024.2"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/> <Option Name="SimulatorVersionModelSim" Val="2024.1"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/> <Option Name="SimulatorVersionQuesta" Val="2024.1"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/> <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/> <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/> <Option Name="SimulatorVersionRiviera" Val="2024.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/> <Option Name="SimulatorVersionActiveHdl" Val="15.0"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/> <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
@ -43,13 +43,13 @@
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/> <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/> <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val="digilentinc.com:arty-a7-35:part0:1.1"/> <Option Name="BoardPart" Val=""/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/> <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="sim_sdspi"/> <Option Name="ActiveSimSet" Val="sim_sdspi"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/> <Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/> <Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PSRCDIR/sources_1"/> <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/> <Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/> <Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/> <Option Name="EnableCoreContainer" Val="FALSE"/>
@ -85,11 +85,11 @@
<Option Name="SimTypes" Val="tlm_dpi"/> <Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/> <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/> <Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/> <Option Name="UseInlineHdlIP" Val="TRUE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration> </Configuration>
<FileSets Version="1" Minor="32"> <FileSets Version="1" Minor="32">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/cpuclk.v"> <File Path="$PSRCDIR/cpuclk.v">
<FileInfo> <FileInfo>
@ -210,7 +210,7 @@
<Option Name="TopModule" Val="top"/> <Option Name="TopModule" Val="top"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR"> <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/> <Filter Type="Constrs"/>
<File Path="$PSRCDIR/Arty-A7-35-Master.xdc"> <File Path="$PSRCDIR/Arty-A7-35-Master.xdc">
<FileInfo> <FileInfo>
@ -223,7 +223,7 @@
<Option Name="ConstrsType" Val="XDC"/> <Option Name="ConstrsType" Val="XDC"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR"> <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/uart_tb.v"/> <File Path="$PSRCDIR/uart_tb.v"/>
<File Path="$PPRDIR/testbench_behav1.wcfg"> <File Path="$PPRDIR/testbench_behav1.wcfg">
@ -246,16 +246,19 @@
<Option Name="SrcSet" Val="sources_1"/> <Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav1.wcfg"/> <Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav1.wcfg"/>
<Option Name="CosimPdi" Val=""/>
<Option Name="CosimPlatform" Val=""/>
<Option Name="CosimElf" Val=""/>
<Option Name="NLNetlistMode" Val="funcsim"/> <Option Name="NLNetlistMode" Val="funcsim"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1"> <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/> <Filter Type="Utils"/>
<Config> <Config>
<Option Name="TopAutoSet" Val="TRUE"/> <Option Name="TopAutoSet" Val="TRUE"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="sim_fifo" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_fifo"> <FileSet Name="sim_fifo" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_fifo" RelGenDir="$PGENDIR/sim_fifo">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/fifo.v"> <File Path="$PSRCDIR/fifo.v">
<FileInfo> <FileInfo>
@ -282,9 +285,12 @@
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/> <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/> <Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/> <Option Name="SrcSet" Val="sources_1"/>
<Option Name="CosimPdi" Val=""/>
<Option Name="CosimPlatform" Val=""/>
<Option Name="CosimElf" Val=""/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="sim_sdspi" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_sdspi"> <FileSet Name="sim_sdspi" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_sdspi" RelGenDir="$PGENDIR/sim_sdspi">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PPRDIR/sdspi_testbench_behav.wcfg"> <File Path="$PPRDIR/sdspi_testbench_behav.wcfg">
<FileInfo> <FileInfo>
@ -305,10 +311,13 @@
<Option Name="PamPseudoTop" Val="pseudo_tb"/> <Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/> <Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/sdspi_testbench_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PPRDIR/sdspi_testbench_behav.wcfg"/>
<Option Name="CosimPdi" Val=""/>
<Option Name="CosimPlatform" Val=""/>
<Option Name="CosimElf" Val=""/>
<Option Name="xsim.simulate.runtime" Val="10ms"/> <Option Name="xsim.simulate.runtime" Val="10ms"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="mig_dram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/mig_dram_0"> <FileSet Name="mig_dram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/mig_dram_0" RelGenDir="$PGENDIR/mig_dram_0">
<File Path="$PSRCDIR/mig_dram_0/mig_dram_0.xci"> <File Path="$PSRCDIR/mig_dram_0/mig_dram_0.xci">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@ -352,7 +361,9 @@
</Run> </Run>
<Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true"> <Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -388,7 +399,9 @@
</Run> </Run>
<Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true"> <Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design"/>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>
@ -404,9 +417,7 @@
<RQSFiles/> <RQSFiles/>
</Run> </Run>
</Runs> </Runs>
<Board> <Board/>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0"> <DashboardSummary Version="1" Minor="0">
<Dashboards> <Dashboards>
<Dashboard Name="default_dashboard"> <Dashboard Name="default_dashboard">