tridoracpu: first attempt at instruction cache
This commit is contained in:
slederer
parent
3f40c50170
commit
b6bd487b7e
5 changed files with 75 additions and 62 deletions
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@ -1,10 +1,10 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2024.1 (64-bit) -->
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<!-- Product Version: Vivado v2024.2.2 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<Project Product="Vivado" Version="7" Minor="67" Path="C:/Users/sebastian/develop/Tridora-NexysA7/Tridora-CPU/tridoracpu/tridoracpu.xpr">
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<Project Product="Vivado" Version="7" Minor="68" Path="C:/Users/sebastian/develop/Tridora-NexysA7/Tridora-CPU/tridoracpu/tridoracpu.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="ab60beb5e7ec4efc9a7b17699b9c3b13"/>
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@ -29,13 +29,13 @@
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<Option Name="SimulatorGccInstallDirVCS" Val=""/>
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<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
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<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorVersionXsim" Val="2024.1"/>
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<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
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<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
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<Option Name="SimulatorVersionXsim" Val="2024.2"/>
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<Option Name="SimulatorVersionModelSim" Val="2024.1"/>
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<Option Name="SimulatorVersionQuesta" Val="2024.1"/>
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<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
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<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
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<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
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<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
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<Option Name="SimulatorVersionRiviera" Val="2024.04"/>
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<Option Name="SimulatorVersionActiveHdl" Val="15.0"/>
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<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
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<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
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@ -43,13 +43,13 @@
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<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
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<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
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<Option Name="BoardPart" Val="digilentinc.com:arty-a7-35:part0:1.1"/>
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<Option Name="BoardPart" Val=""/>
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<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
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<Option Name="ActiveSimSet" Val="sim_sdspi"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="ProjectType" Val="Default"/>
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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<Option Name="IPDefaultOutputPath" Val="$PSRCDIR/sources_1"/>
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<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
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<Option Name="IPCachePermission" Val="read"/>
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<Option Name="IPCachePermission" Val="write"/>
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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@ -85,11 +85,11 @@
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<Option Name="SimTypes" Val="tlm_dpi"/>
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<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
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<Option Name="DcpsUptoDate" Val="TRUE"/>
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<Option Name="ClassicSocBoot" Val="FALSE"/>
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<Option Name="UseInlineHdlIP" Val="TRUE"/>
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<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
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</Configuration>
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<FileSets Version="1" Minor="32">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR" RelGenDir="$PGENDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/cpuclk.v">
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<FileInfo>
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@ -210,7 +210,7 @@
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<Option Name="TopModule" Val="top"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR">
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR" RelGenDir="$PGENDIR/constrs_1">
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<Filter Type="Constrs"/>
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<File Path="$PSRCDIR/Arty-A7-35-Master.xdc">
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<FileInfo>
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@ -223,7 +223,7 @@
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR">
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR" RelGenDir="$PGENDIR/sim_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/uart_tb.v"/>
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<File Path="$PPRDIR/testbench_behav1.wcfg">
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@ -246,16 +246,19 @@
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<Option Name="SrcSet" Val="sources_1"/>
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<Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav.wcfg"/>
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<Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav1.wcfg"/>
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<Option Name="CosimPdi" Val=""/>
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<Option Name="CosimPlatform" Val=""/>
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<Option Name="CosimElf" Val=""/>
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<Option Name="NLNetlistMode" Val="funcsim"/>
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</Config>
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</FileSet>
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
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<Filter Type="Utils"/>
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<Config>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<FileSet Name="sim_fifo" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_fifo">
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<FileSet Name="sim_fifo" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_fifo" RelGenDir="$PGENDIR/sim_fifo">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/fifo.v">
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<FileInfo>
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@ -282,9 +285,12 @@
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<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
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<Option Name="PamPseudoTop" Val="pseudo_tb"/>
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<Option Name="SrcSet" Val="sources_1"/>
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<Option Name="CosimPdi" Val=""/>
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<Option Name="CosimPlatform" Val=""/>
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<Option Name="CosimElf" Val=""/>
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</Config>
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</FileSet>
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<FileSet Name="sim_sdspi" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_sdspi">
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<FileSet Name="sim_sdspi" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_sdspi" RelGenDir="$PGENDIR/sim_sdspi">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/sdspi_testbench_behav.wcfg">
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<FileInfo>
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@ -305,10 +311,13 @@
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<Option Name="PamPseudoTop" Val="pseudo_tb"/>
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<Option Name="SrcSet" Val="sources_1"/>
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<Option Name="XSimWcfgFile" Val="$PPRDIR/sdspi_testbench_behav.wcfg"/>
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<Option Name="CosimPdi" Val=""/>
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<Option Name="CosimPlatform" Val=""/>
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<Option Name="CosimElf" Val=""/>
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<Option Name="xsim.simulate.runtime" Val="10ms"/>
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</Config>
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</FileSet>
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<FileSet Name="mig_dram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/mig_dram_0">
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<FileSet Name="mig_dram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/mig_dram_0" RelGenDir="$PGENDIR/mig_dram_0">
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<File Path="$PSRCDIR/mig_dram_0/mig_dram_0.xci">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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@ -352,7 +361,9 @@
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</Run>
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<Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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@ -388,7 +399,9 @@
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</Run>
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<Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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@ -404,9 +417,7 @@
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<RQSFiles/>
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</Run>
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</Runs>
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<Board>
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<Jumpers/>
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</Board>
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<Board/>
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<DashboardSummary Version="1" Minor="0">
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<Dashboards>
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<Dashboard Name="default_dashboard">
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