tridoracpu: first attempt at instruction cache

tridoracpu/tridoracpu.srcs/stackcpu.v

@@ -11,20 +11,14 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
     output reg [ADDR_WIDTH-1:0] addr,
     input wire [WIDTH-1:0] data_in,
     output wire read_enable,
+    output wire read_ins,
     output wire [WIDTH-1:0] data_out,
     output wire write_enable,
     input wire mem_wait,
     
     output wire led1,
     output wire led2,
-    output wire led3,
-    
-    output wire [WIDTH-1:0] debug_out1,
-    output wire [WIDTH-1:0] debug_out2,
-    output wire [WIDTH-1:0] debug_out3,
-    output wire [WIDTH-1:0] debug_out4,
-    output wire [WIDTH-1:0] debug_out5,
-    output wire [WIDTH-1:0] debug_out6
+    output wire led3
     );
     
     localparam EVAL_STACK_INDEX_WIDTH = 6;
@@ -182,6 +176,8 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
     assign mem_read_enable  = (seq_state == FETCH) || (seq_state == EXEC && mem_read);
     assign mem_write_enable = (seq_state == MEM && mem_write);
     
+    assign read_ins = (seq_state == FETCH) || (seq_state == DECODE);
+ 
     initial
     begin
         PC <= 0; nPC <= 0; seq_state <= MEM;