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tridoracpu: first attempt at instruction cache

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slederer 2025-03-16 00:10:53 +01:00
parent 3f40c50170
commit b6bd487b7e
5 changed files with 75 additions and 62 deletions
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45
tridoracpu/tridoracpu.srcs/dram_bridge.v
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@ -8,6 +8,7 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
input wire [WIDTH-1:0] mem_write_data,
input wire mem_read_enable,
input wire mem_write_enable,
input wire mem_read_ins,
output wire mem_wait,
input wire rst_n,
@ -105,31 +106,35 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
.sys_rst (rst_n)
);
// reg [DRAM_DATA_WIDTH-1:0] read_cache;
// reg [ADDR_WIDTH-1:0] cached_addr;
// wire cache_hit = cached_addr == mem_addr;
// wire [DRAM_DATA_WIDTH-1:0] read_data_wrapper = cache_hit ? read_cache : app_rd_data;
reg [DRAM_DATA_WIDTH-1:0] ins_cache;
reg [DRAM_ADDR_WIDTH-1:4] cached_addr;
wire cache_hit = mem_read_ins && (cached_addr == mem_addr[DRAM_ADDR_WIDTH:4]);
wire [DRAM_DATA_WIDTH-1:0] read_data_wrapper = cache_hit ? ins_cache : app_rd_data;
reg [WIDTH-1:0] read_buf;
reg read_inprogress = 0;
wire dram_read_enable = mem_read_enable && !cache_hit;
assign app_rd_data_end = 1'b1;
//assign app_wdf_mask = 16'b1111111111111100;
// addresses on the memory interface are aligned to 16 bytes
// and 28 bits wide (=256MB)
assign app_addr = { mem_addr[DRAM_ADDR_WIDTH:4], 4'b0000 };
//assign app_addr = { 28'b0 };
// select a word from the 128 bits transferred by the dram controller
// according to the lower bits of the address (ignoring bits 1:0)
wire [WIDTH-1:0] read_word;
wire [1:0] word_sel = mem_addr[3:2];
assign read_word = word_sel == 3'b11 ? app_rd_data[31:0] :
word_sel == 3'b10 ? app_rd_data[63:32] :
word_sel == 3'b01 ? app_rd_data[95:64] :
app_rd_data[127:96];
// assign read_word = word_sel == 3'b11 ? app_rd_data[31:0] :
// word_sel == 3'b10 ? app_rd_data[63:32] :
// word_sel == 3'b01 ? app_rd_data[95:64] :
// app_rd_data[127:96];
assign read_word = word_sel == 3'b11 ? read_data_wrapper[31:0] :
word_sel == 3'b10 ? read_data_wrapper[63:32] :
word_sel == 3'b01 ? read_data_wrapper[95:64] :
read_data_wrapper[127:96];
assign mem_read_data = app_rd_data_valid ? read_word : read_buf;
@ -145,21 +150,31 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
assign app_wdf_end = mem_write_enable & write_ready;
assign app_wdf_data = { {4{mem_write_data}} };
assign mem_wait = (mem_read_enable & ~read_inprogress) |
assign mem_wait = (dram_read_enable & ~read_inprogress) |
(mem_write_enable & (~app_wdf_rdy | ~app_rdy)) |
(read_inprogress & ~app_rd_data_valid);
assign app_en = (mem_read_enable & ~read_inprogress) |
assign app_en = (dram_read_enable & ~read_inprogress) |
(mem_write_enable & write_ready);
assign app_cmd = mem_read_enable ? CMD_READ : CMD_WRITE;
assign app_cmd = dram_read_enable ? CMD_READ : CMD_WRITE;
always @(posedge dram_front_clk)
begin
if(mem_read_enable & ~read_inprogress & app_rdy)
if(mem_read_enable && mem_read_ins && ~cache_hit && app_rd_data_valid)
begin
ins_cache <= mem_read_data;
cached_addr <= mem_addr[DRAM_ADDR_WIDTH:4];
end
end
always @(posedge dram_front_clk)
begin
if(dram_read_enable & ~read_inprogress & app_rdy)
read_inprogress <= 1;
if(read_inprogress & app_rd_data_valid)
read_inprogress <= 0;
if(mem_read_enable & app_rd_data_valid)
if(dram_read_enable & app_rd_data_valid)
read_buf <= mem_read_data;
end
endmodule