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467
tridoraemu/cpu.go
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467
tridoraemu/cpu.go
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// Copyright 2021-2024 Sebastian Lederer. See the file LICENSE.md for details
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package main
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import (
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"fmt"
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"strings"
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)
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type word uint32
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const wordbits = 32
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const wordbytes = 4
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const wordmask = 0xFFFFFFFF
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const hsbmask = 0x80000000
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const estackDepth = 64
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type CPU struct {
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ESP word;
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X word;
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PC, FP,BP,RP word;
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IR,IV word;
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estack [estackDepth] word;
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mem *Mem;
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stopped bool
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trace bool
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singlestep bool
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}
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func sign_extend(bits word, wordbits int) int {
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signmask := word(1 << (wordbits - 1))
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signbit := (bits & signmask) != 0
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// fmt.Printf("sign_extend %b %v signmask %08X signbit %v\n", bits, wordbits, signmask, signbit)
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if signbit {
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return int(bits & ^signmask) - int(signmask)
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} else {
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return int(bits)
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}
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}
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func (c *CPU) initialize() {
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c.ESP = 0
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c.PC = 0
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c.X = 0
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c.FP = 65020 // these are the values set by the ROM monitor
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c.RP = 65024 // for FP and RP
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c.singlestep = false
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}
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func (c *CPU) printEstack() {
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fmt.Printf("[")
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for i := word(1); i <= c.ESP; i++ {
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fmt.Printf(" %08X", c.estack[i])
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}
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fmt.Printf(" %08X ] (%v)\n", c.X, c.ESP)
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}
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func (c *CPU) showStep(desc string, operand int, opWidth int) {
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if !c.trace { return }
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var opStr string
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if opWidth == 0 {
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opStr = ""
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} else {
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opStr = fmt.Sprintf(" %04X", operand)
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}
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fmt.Printf("%08x %-10s%5s ", c.PC, desc, opStr)
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c.printEstack()
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}
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func (c *CPU) getOperand(insWord word, bits int) int {
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return int(insWord & word((1 << bits) - 1))
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}
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func (c *CPU) getSignedOperand(insWord word, bits int) int {
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bitValue := (1 << (bits - 1))
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signBit := insWord & word(bitValue)
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bitMask := (bitValue << 1) - 1
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//fmt.Printf("getSignedOperand bitValue: %v, bitMask: %v\n", bitValue, bitMask)
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o := int(insWord & word(bitMask))
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if signBit != 0 {
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o = int(o) - (bitValue << 1)
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}
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//fmt.Printf("getSignedOperand: %v %v -> %d\n",insWord, bits, o)
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return o
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}
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func (c *CPU) getBit(insWord word, bitnum int) int {
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return int(insWord >> bitnum) & 1
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}
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func (c *CPU) getBits(insWord word, mask word, shiftCount int) word {
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return (insWord & mask) >> shiftCount
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}
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func (c *CPU) getSignedBits(insWord word, mask word, shiftCount int) int {
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result := (insWord & mask) >> shiftCount
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signMask := ((mask >> shiftCount) + 1) >> 1
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//fmt.Printf("getSignedBits %016b signMask %v signBit %v\n", insWord, signMask, insWord & signMask)
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if result & signMask != 0 {
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return - int(result & ^signMask)
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} else {
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return int(result)
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}
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}
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func (c * CPU) addToWord(v word, offset int) word {
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if offset < 0 {
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v -= word(-offset)
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} else {
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v += word(offset)
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}
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return v
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}
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func (c *CPU) step() error {
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nPC := c.PC
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nFP := c.FP
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nBP := c.BP
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nRP := c.RP
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nX := c.X
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nESP := c.ESP
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Y := c.estack[c.ESP]
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insWord, err := c.mem.read(c.PC)
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if err != nil { return err }
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if c.PC % 4 == 0 {
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insWord = insWord >> 16
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} else {
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insWord = insWord & 0xFFFF
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}
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baseIns := insWord >> 13
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nPC += 2
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x2y := false
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deltaESP := 0
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oplen := 0
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switch baseIns {
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// BRANCH
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case 0b000:
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operand := c.getSignedOperand(insWord, 13)
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c.showStep("BRANCH", operand, 13)
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nPC = word(int(c.PC) + operand)
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if operand == 0 {
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fmt.Printf("BRANCH 0 encountered - stopped at PC %08X\n", nPC)
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c.stopped = true
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}
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// ALU
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case 0b001:
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aluop := c.getBits(insWord, 0b0001111000000000, 9)
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deltaESP = c.getSignedBits(insWord, 0b0000000000110000, 4)
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ext := c.getBit(insWord, 7) != 0
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x2y = c.getBit(insWord, 6) != 0
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operand := c.getOperand(insWord, 4)
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// fmt.Printf("aluop %v %v %v %v %v\n", aluop, s, ext, x2y, operand)
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name := "ALU"
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switch aluop {
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case 0:
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name = "ADD"
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nX = c.X + Y
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case 1:
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name = "SUB"
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nX = Y - c.X
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case 2:
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name = "NOT"
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nX = ^ c.X
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case 3:
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name = "AND"
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nX = c.X & Y
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case 4:
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name = "OR"
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nX = c.X | Y
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case 5:
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name = "XOR"
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nX = c.X ^ Y
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case 6:
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name = "CMP"
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oplen = 2
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cmp_i := c.getBit(insWord,2) != 0
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cmp_eq := c.getBit(insWord,1) != 0
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cmp_lt := c.getBit(insWord,0) != 0
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s_x := sign_extend(c.X, wordbits)
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s_y := sign_extend(Y, wordbits)
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result := (cmp_eq && (s_x == s_y)) || (cmp_lt && (s_y < s_x))
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if cmp_i { result = !result }
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if result { nX = 1 } else { nX = 0 }
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case 7:
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name = "Y"
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if !x2y && (deltaESP == -1) { name = "DROP" }
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if x2y && (deltaESP == 0) { name = "SWAP" }
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nX = Y
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case 8:
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name = "SHR"
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nX = c.X >> 1
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if ext {
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nX = nX | (c.X & hsbmask)
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}
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case 9:
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name = "SHL"
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nX = c.X << 1
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if operand & 2 != 0 {
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nX = nX << 1
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}
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oplen = 2
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case 10:
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name = "INC"
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oplen = 4
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if (operand == 0) && (deltaESP == 1) && x2y { name = "DUP" }
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nX = c.X + word(operand)
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case 11:
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name = "DEC"
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oplen = 4
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nX = c.X - word(operand)
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case 12:
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name = "CMPU"
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oplen = 2
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cmp_i := c.getBit(insWord,2) != 0
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cmp_eq := c.getBit(insWord,1) != 0
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cmp_lt := c.getBit(insWord,0) != 0
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result := (cmp_eq && (c.X == Y)) || (cmp_lt && (Y < c.X))
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if cmp_i { result = !result }
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if result { nX = 1 } else { nX = 0 }
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case 13:
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name = "BPLC"
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nX = (c.X & 0xFF) << ((3 - (Y & 3)) * 8)
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case 14:
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name = "BROT"
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nX = ((c.X & 0x00FFFFFF) << 8 ) | ((c.X & 0xFF000000) >> 24)
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case 15:
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name = "BSEL"
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shift := (3 - (Y & 3)) * 8
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nX = (c.X >> shift) & 0xFF
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}
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c.showStep(name, operand, oplen)
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// STORE
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case 0b010:
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operand := c.getOperand(insWord, 13)
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var ea word
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var name string
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if (insWord & 1) == 1 {
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name = "STORE.B"
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ea = c.BP + word(operand)
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} else {
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name = "STORE"
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ea = c.FP + word(operand)
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}
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c.showStep(name, operand, oplen)
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err = c.mem.write(c.X, ea)
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if err != nil { return err }
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deltaESP = -1
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nX = Y
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// XFER
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case 0b011:
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var name string
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deltaRP := c.getSignedBits(insWord, 0b0000001100000000, 8)
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deltaESP = c.getSignedBits(insWord, 0b0000000000110000, 4)
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r2p := c.getBit(insWord, 7) != 0
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p2r := c.getBit(insWord, 6) != 0
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x2p := c.getBit(insWord, 0) != 0
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if deltaRP >= 0 {
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nRP = c.RP + word(deltaRP * wordbytes)
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} else {
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nRP = c.RP - word(-deltaRP * wordbytes)
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}
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if (deltaRP == 1) && (deltaESP == -1) && p2r && x2p {
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name = "CALL"
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} else
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if (deltaRP == -1) && (deltaESP == 0) && r2p {
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name = "RET"
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} else
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if (deltaRP == 0) && (deltaESP == -1) && x2p && !p2r {
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name = "JUMP"
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} else {
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var b strings.Builder
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b.WriteString("XFER")
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if deltaRP == -1 { b.WriteString(".RSM1") }
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if deltaRP == 1 { b.WriteString(".RS1") }
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if deltaESP == -1 { b.WriteString(".SM1") }
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if deltaESP == 1 { b.WriteString(".S1") }
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if r2p { b.WriteString(".R2P") }
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if p2r { b.WriteString(".P2R") }
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if x2p { b.WriteString(".X2P") }
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name = b.String()
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}
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c.showStep(name, 0, 0)
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if r2p {
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nPC, err = c.mem.read(c.RP)
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if err != nil { return err }
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}
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if p2r {
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err = c.mem.write(nPC, nRP)
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if err != nil { return err }
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}
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if x2p {
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nPC = c.X
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nX = Y
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}
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// LOAD
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case 0b100:
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operand := c.getOperand(insWord, 13)
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var ea word
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var name string
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if (insWord & 1) == 1 {
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name = "LOAD.B"
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operand &= ^1
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ea = c.BP + word(operand)
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} else {
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name = "LOAD"
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ea = c.FP + word(operand)
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}
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c.showStep(name, operand, oplen)
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deltaESP = 1
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x2y = true
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nX, err = c.mem.read(ea)
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if err != nil { return err }
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// CBRANCH
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case 0b101:
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operand := c.getSignedOperand(insWord, 13)
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var name string
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invert := (operand & 1) == 0
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operand = operand & -2 // clear bit 0
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if invert { name = "CBRANCH.Z" } else { name = "CBRANCH" }
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c.showStep(name, operand, 13)
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deltaESP = -1
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nX = Y
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if (c.X != 0 && !invert) || (c.X == 0 && invert) {
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nPC = word(int(c.PC) + operand)
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}
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// LOADC
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case 0b110:
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operand := c.getSignedOperand(insWord, 13)
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oplen = 13
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c.showStep("LOADC", operand, oplen)
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deltaESP = 1
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x2y = true
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nX = word(operand)
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// EXT
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case 0b111:
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extop := c.getBits(insWord, 0b0001111000000000, 10)
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deltaESP = c.getSignedBits(insWord, 0b0000000000110000, 4)
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writeFlag := c.getBit(insWord, 9) != 0
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// signExtend := c.getBit(insWord,7) != 0
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x2y = c.getBit(insWord, 6) != 0
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operand := c.getOperand(insWord, 4)
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var name string
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switch extop {
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// LOADREG/STOREREG
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case 0:
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oplen = 4
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if writeFlag {
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name = "STOREREG"
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switch operand {
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case 0: nFP = c.X
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case 1: nBP = c.X
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case 2: nRP = c.X
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case 3: c.IV = c.X // should be nIV
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case 4: c.IR = c.X // should be nIR
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default: fmt.Errorf("Invalid STOREREG operand %v at %08X", operand, c.PC)
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}
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c.showStep(name, operand, oplen)
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deltaESP = -1
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x2y = false
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nX = Y
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} else {
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name = "LOADREG"
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switch operand {
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case 0: nX = c.FP
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case 1: nX = c.BP
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case 2: nX = c.RP
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case 3: nX = c.IV
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case 4: nX = c.IR
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case 5: nX = c.ESP
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default: fmt.Errorf("Invalid LOADREG operand %v at %08X", operand, c.PC)
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}
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c.showStep(name, operand, oplen)
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deltaESP = 1
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x2y = true
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}
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// LOADI/STOREI
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case 1:
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if writeFlag { name = "STOREI" } else { name = "LOADI" }
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c.showStep(name, operand, oplen)
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if writeFlag {
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oplen = 4
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err = c.mem.write(c.X, Y)
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if err != nil { return err }
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nX = Y + word(operand)
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} else {
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nX, err = c.mem.read(c.X)
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if err != nil { return err }
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}
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// FPADJ
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case 3:
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operand := c.getSignedOperand(insWord, 10)
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oplen = 10
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nFP = c.FP + word(operand)
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deltaESP = 0
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x2y = false
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c.showStep("FPADJ", operand, oplen)
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// LOADREL
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case 5:
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offset := c.getOperand(insWord, 10)
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c.showStep("LOADREL", offset, 10)
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nX, err = c.mem.read(c.PC + word(offset))
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if err != nil { return err }
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x2y = true
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deltaESP = 1
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default:
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return fmt.Errorf("Invalid EXT instruction %v at %08X", extop, c.PC)
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}
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default:
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return fmt.Errorf("Invalid instruction %04X at %08X", insWord, c.PC)
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}
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nESP = c.addToWord(nESP, deltaESP)
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if nESP < 0 || nESP >= estackDepth {
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return fmt.Errorf("estack overflow %v at %08X", nESP, c.PC)
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}
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if x2y {
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c.estack[nESP] = c.X
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}
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c.PC = nPC
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c.FP = nFP
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c.BP = nBP
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c.X = nX
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c.RP = nRP
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c.ESP = nESP
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return nil
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}
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