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Merge branch 'inscache' of ssh://forgejo@git.insignificance.de:42122/slederer/Tridora-CPU.git

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# Conflicts:
#	examples/benchmarks.results.text
This commit is contained in:
slederer 2025-04-13 23:21:38 +02:00
commit a060b65bb9
14 changed files with 168 additions and 109 deletions
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1
.gitignore vendored
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@ -33,6 +33,7 @@ pcomp/sdis
tridoraemu/tridoraemu tridoraemu/tridoraemu
**/tridoracpu.cache/ **/tridoracpu.cache/
**/tridoracpu.hw/ **/tridoracpu.hw/
**/tridoracpu.gen/
**/tridoracpu.ip_user_files/ **/tridoracpu.ip_user_files/
**/tridoracpu.runs/ **/tridoracpu.runs/
*.log *.log

1
examples/benchmarks.results.text
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@ -91,4 +91,3 @@ Running benchmarks.prog
array copy 128k 1K 00:00:48 array copy 128k 1K 00:00:48
exp() 10K 00:00:32 exp() 10K 00:00:32
cos() 10K 00:00:06 cos() 10K 00:00:06

16
lib/corelib.s
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@ -588,13 +588,19 @@ DIVU_END:
; wait approx. 1 millisecond ; wait approx. 1 millisecond
; ;
; 83.333 MHz Clock, three instructions a 4 cycles ; the ROM at address 4
; 83333 / 12 = 6944.4166 ; contains the cpu clock freq in KHz
; works only if executed without wait states (i.e. .EQU CLK_KHZ_ADDR 4
; from BRAM/SRAM)
WAIT1MSEC: WAIT1MSEC:
LOADCP 6944 LOADC CLK_KHZ_ADDR
LOADI
; divide by 16
SHR
SHR
SHR
SHR
WAIT1LOOP: WAIT1LOOP:
INC 0 ; NOP to make the loop 16 cycles long
DEC 1 DEC 1
DUP DUP
CBRANCH.NZ WAIT1LOOP CBRANCH.NZ WAIT1LOOP

24
lib/rommon.s
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@ -7,8 +7,16 @@
.EQU UART_REG 2048 .EQU UART_REG 2048
.EQU MON_ADDR 64512 .EQU MON_ADDR 64512
.EQU CLK_KHZ 76923
BRANCH 2 ; the very first instruction is not BRANCH 2 ; the very first instruction is not
; executed correctly ; executed correctly
BRANCH MON_START ; branch over constant
CLK_KHZ_ADDR:
.WORD CLK_KHZ ; to calibrate the delay loop
MON_START:
LOADCP 65020 ; initialise FP and RP registers LOADCP 65020 ; initialise FP and RP registers
STOREREG FP STOREREG FP
LOADCP 65024 LOADCP 65024
@ -782,13 +790,17 @@ COPY_BLK1:
; wait approx. 1 millisecond ; wait approx. 1 millisecond
; ;
; 83.333 MHz Clock, three instructions a 4 cycles
; 83333 / 12 = 6944.4166
; works only if executed without wait states (i.e.
; from BRAM/SRAM)
WAIT1MSEC: WAIT1MSEC:
LOADCP 6944 ; get clock freq in khz
LOADC CLK_KHZ_ADDR
LOADI
; divide by 16
SHR
SHR
SHR
SHR
WAIT1LOOP: WAIT1LOOP:
INC 0 ; NOP to make loop 16 cycles long
DEC 1 DEC 1
DUP DUP
CBRANCH.NZ WAIT1LOOP CBRANCH.NZ WAIT1LOOP
@ -798,7 +810,7 @@ WAIT1LOOP:
%include "sdcardboot.s" %include "sdcardboot.s"
.CPOOL .CPOOL
MESSAGE: MESSAGE:
.BYTE 13,10,"ROM Monitor v3.0.3", 13, 10, .BYTE 13,10,"ROM Monitor v3.1.0", 13, 10,
"Set A)ddress D)eposit eX)amine L)oad G)o B)oot",13,10,0 "Set A)ddress D)eposit eX)amine L)oad G)o B)oot",13,10,0
PROMPT2: PROMPT2:
.BYTE "]> ",0 .BYTE "]> ",0

2
tridoracpu/tridoracpu.srcs/Arty-A7-35-Master.xdc
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@ -216,3 +216,5 @@ set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports rst]
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10] #set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
set_property BITSTREAM.GENERAL.COMPRESS True [current_design] set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
set_max_delay -from [get_pins vgafb0/display_timings_inst/o_vblank_reg/C] -to [get_pins vgafb0/vblank_xfer_reg/D] 3.000

4
tridoracpu/tridoracpu.srcs/cpuclk.v
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@ -17,7 +17,9 @@ module cpu_clkgen(
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000). .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000).
.CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). .CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128) // CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
.CLKOUT0_DIVIDE_F(12.0), // Divide amount for CLKOUT0 (1.000-128.000). // CPU Clock: 12.0 = 83.33MHz CPU Clock, 333.33MHz Memory Clock
// 13.0 = 76.92MHz CPU Clock, 307.69MHz Memory Clock
.CLKOUT0_DIVIDE_F(13.0), // Divide amount for CLKOUT0 (1.000-128.000).
.CLKOUT1_DIVIDE(5), .CLKOUT1_DIVIDE(5),
.CLKOUT2_DIVIDE(40), // 40 = 25MHz pixel clock (should be 25.175MHz per spec) for 640x480 .CLKOUT2_DIVIDE(40), // 40 = 25MHz pixel clock (should be 25.175MHz per spec) for 640x480
//.CLKOUT2_DIVIDE(25), // 25 = 40MHz pixel clock for 800x600 //.CLKOUT2_DIVIDE(25), // 25 = 40MHz pixel clock for 800x600

47
tridoracpu/tridoracpu.srcs/dram_bridge.v
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@ -8,6 +8,7 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
input wire [WIDTH-1:0] mem_write_data, input wire [WIDTH-1:0] mem_write_data,
input wire mem_read_enable, input wire mem_read_enable,
input wire mem_write_enable, input wire mem_write_enable,
input wire mem_read_ins,
output wire mem_wait, output wire mem_wait,
input wire rst_n, input wire rst_n,
@ -105,33 +106,38 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
.sys_rst (rst_n) .sys_rst (rst_n)
); );
// reg [DRAM_DATA_WIDTH-1:0] read_cache; (*KEEP*) reg [DRAM_DATA_WIDTH-1:0] ins_cache;
// reg [ADDR_WIDTH-1:0] cached_addr; (*KEEP*) reg [DRAM_ADDR_WIDTH-1:4] cached_addr;
// wire cache_hit = cached_addr == mem_addr; (*KEEP*) wire cache_hit = mem_read_enable && mem_read_ins && (cached_addr == mem_addr[DRAM_ADDR_WIDTH-1:4]);
// wire [DRAM_DATA_WIDTH-1:0] read_data_wrapper = cache_hit ? read_cache : app_rd_data;
reg [WIDTH-1:0] read_buf; reg [WIDTH-1:0] read_buf;
reg read_inprogress = 0; reg read_inprogress = 0;
wire dram_read_enable = mem_read_enable && !cache_hit;
assign app_rd_data_end = 1'b1; assign app_rd_data_end = 1'b1;
//assign app_wdf_mask = 16'b1111111111111100;
// addresses on the memory interface are aligned to 16 bytes // addresses on the memory interface are aligned to 16 bytes
// and 28 bits wide (=256MB) // and 28 bits wide (=256MB)
assign app_addr = { mem_addr[DRAM_ADDR_WIDTH:4], 4'b0000 }; assign app_addr = { mem_addr[DRAM_ADDR_WIDTH:4], 4'b0000 };
//assign app_addr = { 28'b0 };
// select a word from the 128 bits transferred by the dram controller // select a word from the 128 bits transferred by the dram controller
// according to the lower bits of the address (ignoring bits 1:0) // according to the lower bits of the address (ignoring bits 1:0)
wire [WIDTH-1:0] read_word;
wire [1:0] word_sel = mem_addr[3:2]; wire [1:0] word_sel = mem_addr[3:2];
assign read_word = word_sel == 3'b11 ? app_rd_data[31:0] : wire [WIDTH-1:0] read_word =
word_sel == 3'b11 ? app_rd_data[31:0] :
word_sel == 3'b10 ? app_rd_data[63:32] : word_sel == 3'b10 ? app_rd_data[63:32] :
word_sel == 3'b01 ? app_rd_data[95:64] : word_sel == 3'b01 ? app_rd_data[95:64] :
app_rd_data[127:96]; app_rd_data[127:96];
assign mem_read_data = app_rd_data_valid ? read_word : read_buf; wire [WIDTH-1:0] read_cached_word =
word_sel == 3'b11 ? ins_cache[31:0] :
word_sel == 3'b10 ? ins_cache[63:32] :
word_sel == 3'b01 ? ins_cache[95:64] :
ins_cache[127:96];
(*KEEP*) assign mem_read_data = cache_hit ? read_cached_word :
app_rd_data_valid ? read_word : read_buf;
// set the write mask according to the lower bits of the address // set the write mask according to the lower bits of the address
// (ignoring bit 0) // (ignoring bit 0)
@ -145,21 +151,34 @@ module dram_bridge #(ADDR_WIDTH = 32, WIDTH = 32)
assign app_wdf_end = mem_write_enable & write_ready; assign app_wdf_end = mem_write_enable & write_ready;
assign app_wdf_data = { {4{mem_write_data}} }; assign app_wdf_data = { {4{mem_write_data}} };
assign mem_wait = (mem_read_enable & ~read_inprogress) | assign mem_wait = (dram_read_enable & ~read_inprogress) |
(mem_write_enable & (~app_wdf_rdy | ~app_rdy)) | (mem_write_enable & (~app_wdf_rdy | ~app_rdy)) |
(read_inprogress & ~app_rd_data_valid); (read_inprogress & ~app_rd_data_valid);
assign app_en = (mem_read_enable & ~read_inprogress) | assign app_en = (dram_read_enable & ~read_inprogress) |
(mem_write_enable & write_ready); (mem_write_enable & write_ready);
assign app_cmd = mem_read_enable ? CMD_READ : CMD_WRITE; assign app_cmd = dram_read_enable ? CMD_READ : CMD_WRITE;
always @(posedge dram_front_clk) always @(posedge dram_front_clk)
begin begin
if(mem_read_enable & ~read_inprogress & app_rdy) if(dram_read_enable && mem_read_ins && app_rd_data_valid)
begin
ins_cache <= app_rd_data;
cached_addr <= mem_addr[DRAM_ADDR_WIDTH-1:4];
end
end
always @(posedge dram_front_clk)
begin
if(dram_read_enable & ~read_inprogress & app_rdy)
read_inprogress <= 1; read_inprogress <= 1;
if(read_inprogress & app_rd_data_valid) if(read_inprogress & app_rd_data_valid)
read_inprogress <= 0; read_inprogress <= 0;
if(mem_read_enable & app_rd_data_valid) if(dram_read_enable & app_rd_data_valid)
read_buf <= mem_read_data; read_buf <= mem_read_data;
else
if (mem_read_enable & cache_hit)
read_buf <= read_cached_word;
end end
endmodule endmodule

6
tridoracpu/tridoracpu.srcs/mig_dram_0/mig_a.prj
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@ -39,12 +39,12 @@
<Controller number="0"> <Controller number="0">
<MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice> <MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
<TimePeriod>3000</TimePeriod> <TimePeriod>3300</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO> <VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio> <PHYRatio>4:1</PHYRatio>
<InputClkFreq>83.333</InputClkFreq> <InputClkFreq>75.757</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks> <UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>666</MMCM_VCO> <MMCM_VCO>606</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0> <MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1> <MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2> <MMCMClkOut2>1</MMCMClkOut2>

6
tridoracpu/tridoracpu.srcs/mig_dram_0/mig_b.prj
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@ -39,12 +39,12 @@
<Controller number="0"> <Controller number="0">
<MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice> <MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
<TimePeriod>3000</TimePeriod> <TimePeriod>3250</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO> <VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio> <PHYRatio>4:1</PHYRatio>
<InputClkFreq>83.333</InputClkFreq> <InputClkFreq>76.923</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks> <UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>666</MMCM_VCO> <MMCM_VCO>615</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0> <MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1> <MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2> <MMCMClkOut2>1</MMCMClkOut2>

2
tridoracpu/tridoracpu.srcs/sdspi.v
View file

@ -107,7 +107,7 @@ module sdspi(
tx_fifo_empty tx_fifo_empty
); );
fifo #(.ADDR_WIDTH(8)) rx_fifo(clk, reset, fifo #(.ADDR_WIDTH(10)) rx_fifo(clk, reset,
rx_fifo_wr_en, rx_fifo_rd_en, rx_fifo_wr_en, rx_fifo_rd_en,
rx_shifter, rx_fifo_out, rx_shifter, rx_fifo_out,
rx_fifo_full, rx_fifo_full,

12
tridoracpu/tridoracpu.srcs/stackcpu.v
View file

@ -11,20 +11,14 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
output reg [ADDR_WIDTH-1:0] addr, output reg [ADDR_WIDTH-1:0] addr,
input wire [WIDTH-1:0] data_in, input wire [WIDTH-1:0] data_in,
output wire read_enable, output wire read_enable,
output wire read_ins,
output wire [WIDTH-1:0] data_out, output wire [WIDTH-1:0] data_out,
output wire write_enable, output wire write_enable,
input wire mem_wait, input wire mem_wait,
output wire led1, output wire led1,
output wire led2, output wire led2,
output wire led3, output wire led3
output wire [WIDTH-1:0] debug_out1,
output wire [WIDTH-1:0] debug_out2,
output wire [WIDTH-1:0] debug_out3,
output wire [WIDTH-1:0] debug_out4,
output wire [WIDTH-1:0] debug_out5,
output wire [WIDTH-1:0] debug_out6
); );
localparam EVAL_STACK_INDEX_WIDTH = 6; localparam EVAL_STACK_INDEX_WIDTH = 6;
@ -182,6 +176,8 @@ module stackcpu #(parameter ADDR_WIDTH = 32, WIDTH = 32,
assign mem_read_enable = (seq_state == FETCH) || (seq_state == EXEC && mem_read); assign mem_read_enable = (seq_state == FETCH) || (seq_state == EXEC && mem_read);
assign mem_write_enable = (seq_state == MEM && mem_write); assign mem_write_enable = (seq_state == MEM && mem_write);
assign read_ins = (seq_state == FETCH) || (seq_state == DECODE);
initial initial
begin begin
PC <= 0; nPC <= 0; seq_state <= MEM; PC <= 0; nPC <= 0; seq_state <= MEM;

27
tridoracpu/tridoracpu.srcs/top.v
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@ -3,7 +3,8 @@
// or as clk_1hz for debugging // or as clk_1hz for debugging
`define clock cpuclk `define clock cpuclk
`define clkfreq 83333333 //`define clkfreq 83333333
`define clkfreq 76923076
//`define clock clk //`define clock clk
//`define clkfreq 100000000 //`define clkfreq 100000000
//`define clock clk_1hz //`define clock clk_1hz
@ -67,10 +68,11 @@ module top(
localparam ADDR_WIDTH = 32, WIDTH = 32, localparam ADDR_WIDTH = 32, WIDTH = 32,
ROMADDR_WIDTH = 11, IOADDR_WIDTH = 11, IOADDR_SEL = 4; ROMADDR_WIDTH = 11, IOADDR_WIDTH = 11, IOADDR_SEL = 4;
wire [ADDR_WIDTH-1:0] mem_addr; (* KEEP *) wire [ADDR_WIDTH-1:0] mem_addr;
wire [WIDTH-1:0] mem_read_data; wire [WIDTH-1:0] mem_read_data;
wire [WIDTH-1:0] mem_write_data; wire [WIDTH-1:0] mem_write_data;
(* KEEP *) wire mem_wait; (* KEEP *) wire mem_wait;
assign led0 = mem_wait;
(* KEEP *) wire mem_read_enable; (* KEEP *) wire mem_read_enable;
(* KEEP *) wire mem_write_enable; (* KEEP *) wire mem_write_enable;
@ -80,14 +82,6 @@ module top(
wire irq; wire irq;
// assign led0 = mem_wait;
wire [WIDTH-1:0] debug_data1, debug_data2,
debug_data3, debug_data4,
debug_data5, debug_data6;
assign led0 = debug_data6[0];
wire cpuclk, cpuclk_locked; wire cpuclk, cpuclk_locked;
wire dram_refclk200; wire dram_refclk200;
wire pixclk; wire pixclk;
@ -97,9 +91,11 @@ module top(
wire [ADDR_WIDTH-1:0] dram_addr; wire [ADDR_WIDTH-1:0] dram_addr;
wire [WIDTH-1:0] dram_read_data, dram_write_data; wire [WIDTH-1:0] dram_read_data, dram_write_data;
wire dram_read_enable, dram_write_enable, dram_wait; wire dram_read_enable, dram_write_enable, dram_wait;
(* KEEP *) wire dram_read_ins;
dram_bridge dram_bridge0 (dram_addr, dram_bridge dram_bridge0 (dram_addr,
dram_read_data, dram_write_data, dram_read_enable, dram_write_enable, dram_wait, dram_read_data, dram_write_data, dram_read_enable, dram_write_enable,
dram_read_ins, dram_wait,
rst, cpuclk, dram_refclk200, rst, cpuclk, dram_refclk200,
ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr, ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr,
ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n,
@ -254,15 +250,10 @@ module top(
stackcpu cpu0(.clk(`clock), .rst(rst), .irq(irq), stackcpu cpu0(.clk(`clock), .rst(rst), .irq(irq),
.addr(mem_addr), .addr(mem_addr),
.data_in(mem_read_data), .read_enable(mem_read_enable), .data_in(mem_read_data), .read_enable(mem_read_enable),
.read_ins(dram_read_ins),
.data_out(mem_write_data), .write_enable(mem_write_enable), .data_out(mem_write_data), .write_enable(mem_write_enable),
.mem_wait(mem_wait), .mem_wait(mem_wait),
.led1(led1), .led2(led2), .led3(led3), .led1(led1), .led2(led2), .led3(led3));
.debug_out1(debug_data1),
.debug_out2(debug_data2),
.debug_out3(debug_data3),
.debug_out4(debug_data4),
.debug_out5(debug_data5),
.debug_out6(debug_data6));
// Interrupt Controller // Interrupt Controller
irqctrl irqctrl0(`clock, irq_in, irqc_cs, mem_write_enable, irqctrl irqctrl0(`clock, irq_in, irqc_cs, mem_write_enable,

8
tridoracpu/tridoracpu.srcs/vgafb.v
View file

@ -62,10 +62,11 @@ module display_timings #(
// o_scanline: high for one tick at the start of each visible scanline // o_scanline: high for one tick at the start of each visible scanline
assign o_scanline = (o_sy >= VA_STA) && (o_sy <= VA_END) && (o_sx == H_STA); assign o_scanline = (o_sy >= VA_STA) && (o_sy <= VA_END) && (o_sx == H_STA);
// set vblank at end of frame, clear at start
always @(posedge i_pix_clk) always @(posedge i_pix_clk)
begin begin
if(o_frame) o_vblank <= 1; if(o_sy == VA_END) o_vblank <= 1;
else if (o_de) o_vblank <= 0; else if (o_sy == -1) o_vblank <= 0;
end end
always @ (posedge i_pix_clk) always @ (posedge i_pix_clk)
@ -175,6 +176,7 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
wire scanline; // scanline start wire scanline; // scanline start
wire vblank; // vertical blank wire vblank; // vertical blank
reg vblank_buf; // vertical blank in cpu clock domain reg vblank_buf; // vertical blank in cpu clock domain
reg vblank_xfer; // vertical blank clock domain crossing
display_timings #( // 640x480 800x600 1280x720 1920x1080 display_timings #( // 640x480 800x600 1280x720 1920x1080
`ifdef RES_1024_768 `ifdef RES_1024_768
@ -233,7 +235,7 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
always @(posedge pix_clk) frame_d <= frame; always @(posedge pix_clk) frame_d <= frame;
always @(posedge cpu_clk) vblank_buf <= vblank; always @(posedge cpu_clk) { vblank_buf, vblank_xfer } <= { vblank_xfer, vblank };
always @(posedge cpu_clk) always @(posedge cpu_clk)
begin begin

121
tridoracpu/tridoracpu.xpr
View file

@ -1,9 +1,10 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.1 (64-bit) --> <!-- Product Version: Vivado v2024.2.2 (64-bit) -->
<!-- --> <!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Version="7" Minor="49" Path="./tridoracpu.xpr"> <Project Product="Vivado" Version="7" Minor="68" Path="C:/Users/sebastian/develop/Tridora-NexysA7/Tridora-CPU/tridoracpu/tridoracpu.xpr">
<DefaultLaunch Dir="$PRUNDIR"/> <DefaultLaunch Dir="$PRUNDIR"/>
<Configuration> <Configuration>
<Option Name="Id" Val="ab60beb5e7ec4efc9a7b17699b9c3b13"/> <Option Name="Id" Val="ab60beb5e7ec4efc9a7b17699b9c3b13"/>
@ -12,29 +13,48 @@
<Option Name="CompiledLibDirXSim" Val=""/> <Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/> <Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/> <Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirIES" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/> <Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/> <Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/> <Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/> <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="BoardPart" Val="digilentinc.com:arty-a7-35:part0:1.0"/> <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../AppData/Roaming/Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store"/> <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2024.2"/>
<Option Name="SimulatorVersionModelSim" Val="2024.1"/>
<Option Name="SimulatorVersionQuesta" Val="2024.1"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2024.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="15.0"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val=""/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/> <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="sim_sdspi"/> <Option Name="ActiveSimSet" Val="sim_sdspi"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/> <Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/> <Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PSRCDIR/sources_1"/> <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/> <Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/> <Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/> <Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
@ -47,13 +67,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/> <Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/> <Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/> <Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="4"/> <Option Name="WTXSimExportSim" Val="6"/>
<Option Name="WTModelSimExportSim" Val="4"/> <Option Name="WTModelSimExportSim" Val="6"/>
<Option Name="WTQuestaExportSim" Val="4"/> <Option Name="WTQuestaExportSim" Val="6"/>
<Option Name="WTIesExportSim" Val="4"/> <Option Name="WTIesExportSim" Val="4"/>
<Option Name="WTVcsExportSim" Val="4"/> <Option Name="WTVcsExportSim" Val="6"/>
<Option Name="WTRivieraExportSim" Val="4"/> <Option Name="WTRivieraExportSim" Val="6"/>
<Option Name="WTActivehdlExportSim" Val="4"/> <Option Name="WTActivehdlExportSim" Val="6"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/> <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/> <Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/> <Option Name="XSimTimeUnit" Val="ns"/>
@ -65,9 +85,11 @@
<Option Name="SimTypes" Val="tlm_dpi"/> <Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/> <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/> <Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="UseInlineHdlIP" Val="TRUE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration> </Configuration>
<FileSets Version="1" Minor="31"> <FileSets Version="1" Minor="32">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/cpuclk.v"> <File Path="$PSRCDIR/cpuclk.v">
<FileInfo> <FileInfo>
@ -188,7 +210,7 @@
<Option Name="TopModule" Val="top"/> <Option Name="TopModule" Val="top"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR"> <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/> <Filter Type="Constrs"/>
<File Path="$PSRCDIR/Arty-A7-35-Master.xdc"> <File Path="$PSRCDIR/Arty-A7-35-Master.xdc">
<FileInfo> <FileInfo>
@ -201,7 +223,7 @@
<Option Name="ConstrsType" Val="XDC"/> <Option Name="ConstrsType" Val="XDC"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR"> <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/uart_tb.v"/> <File Path="$PSRCDIR/uart_tb.v"/>
<File Path="$PPRDIR/testbench_behav1.wcfg"> <File Path="$PPRDIR/testbench_behav1.wcfg">
@ -224,28 +246,19 @@
<Option Name="SrcSet" Val="sources_1"/> <Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav1.wcfg"/> <Option Name="XSimWcfgFile" Val="$PPRDIR/testbench_behav1.wcfg"/>
<Option Name="CosimPdi" Val=""/>
<Option Name="CosimPlatform" Val=""/>
<Option Name="CosimElf" Val=""/>
<Option Name="NLNetlistMode" Val="funcsim"/> <Option Name="NLNetlistMode" Val="funcsim"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1"> <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/> <Filter Type="Utils"/>
<Config> <Config>
<Option Name="TopAutoSet" Val="TRUE"/> <Option Name="TopAutoSet" Val="TRUE"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="mig_dram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/mig_dram_0"> <FileSet Name="sim_fifo" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_fifo" RelGenDir="$PGENDIR/sim_fifo">
<File Path="$PSRCDIR/mig_dram_0/mig_dram_0.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="mig_dram_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="sim_fifo" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_fifo">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/fifo.v"> <File Path="$PSRCDIR/fifo.v">
<FileInfo> <FileInfo>
@ -272,9 +285,12 @@
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/> <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/> <Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/> <Option Name="SrcSet" Val="sources_1"/>
<Option Name="CosimPdi" Val=""/>
<Option Name="CosimPlatform" Val=""/>
<Option Name="CosimElf" Val=""/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="sim_sdspi" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_sdspi"> <FileSet Name="sim_sdspi" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_sdspi" RelGenDir="$PGENDIR/sim_sdspi">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PPRDIR/sdspi_testbench_behav.wcfg"> <File Path="$PPRDIR/sdspi_testbench_behav.wcfg">
<FileInfo> <FileInfo>
@ -295,9 +311,24 @@
<Option Name="PamPseudoTop" Val="pseudo_tb"/> <Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/> <Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/sdspi_testbench_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PPRDIR/sdspi_testbench_behav.wcfg"/>
<Option Name="CosimPdi" Val=""/>
<Option Name="CosimPlatform" Val=""/>
<Option Name="CosimElf" Val=""/>
<Option Name="xsim.simulate.runtime" Val="10ms"/> <Option Name="xsim.simulate.runtime" Val="10ms"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="mig_dram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/mig_dram_0" RelGenDir="$PGENDIR/mig_dram_0">
<File Path="$PSRCDIR/mig_dram_0/mig_dram_0.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="mig_dram_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets> </FileSets>
<Simulators> <Simulators>
<Simulator Name="XSim"> <Simulator Name="XSim">
@ -317,8 +348,8 @@
<Option Name="Description" Val="Active-HDL Simulator"/> <Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator> </Simulator>
</Simulators> </Simulators>
<Runs Version="1" Minor="11"> <Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/> <Step Id="synth_design"/>
@ -328,17 +359,17 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true"> <Run Id="mig_dram_0_synth_1" Type="Ft3:Synth" SrcSet="mig_dram_0" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_dram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/> <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Increase placer effort in the post-placement optimization phase, and disable timing relaxation in the router." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Increase placer effort in the post-placement optimization phase, and disable timing relaxation in the router." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Performance_RefinePlacement" Flow="Vivado Implementation 2020"/> <StratHandle Name="Performance_RefinePlacement" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/> <Step Id="init_design"/>
@ -364,9 +395,9 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" GenFullBitstream="true"> <Run Id="mig_dram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="mig_dram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_dram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/mig_dram_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design"/>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>
@ -377,14 +408,12 @@
<Step Id="post_route_phys_opt_design"/> <Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/> <Step Id="write_bitstream"/>
</Strategy> </Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
</Runs> </Runs>
<Board> <Board/>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0"> <DashboardSummary Version="1" Minor="0">
<Dashboards> <Dashboards>
<Dashboard Name="default_dashboard"> <Dashboard Name="default_dashboard">