slederer/Tridora-CPU
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Merge branch 'inscache' of ssh://forgejo@git.insignificance.de:42122/slederer/Tridora-CPU.git

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# Conflicts:
#	examples/benchmarks.results.text
This commit is contained in:
slederer 2025-04-13 23:21:38 +02:00
commit a060b65bb9
14 changed files with 168 additions and 109 deletions
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16
lib/corelib.s
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@ -588,13 +588,19 @@ DIVU_END:
; wait approx. 1 millisecond
;
; 83.333 MHz Clock, three instructions a 4 cycles
; 83333 / 12 = 6944.4166
; works only if executed without wait states (i.e.
; from BRAM/SRAM)
; the ROM at address 4
; contains the cpu clock freq in KHz
.EQU CLK_KHZ_ADDR 4
WAIT1MSEC:
LOADCP 6944
LOADC CLK_KHZ_ADDR
LOADI
; divide by 16
SHR
SHR
SHR
SHR
WAIT1LOOP:
INC 0 ; NOP to make the loop 16 cycles long
DEC 1
DUP
CBRANCH.NZ WAIT1LOOP

24
lib/rommon.s
View file

@ -7,8 +7,16 @@
.EQU UART_REG 2048
.EQU MON_ADDR 64512
.EQU CLK_KHZ 76923
BRANCH 2 ; the very first instruction is not
; executed correctly
BRANCH MON_START ; branch over constant
CLK_KHZ_ADDR:
.WORD CLK_KHZ ; to calibrate the delay loop
MON_START:
LOADCP 65020 ; initialise FP and RP registers
STOREREG FP
LOADCP 65024
@ -782,13 +790,17 @@ COPY_BLK1:
; wait approx. 1 millisecond
;
; 83.333 MHz Clock, three instructions a 4 cycles
; 83333 / 12 = 6944.4166
; works only if executed without wait states (i.e.
; from BRAM/SRAM)
WAIT1MSEC:
LOADCP 6944
; get clock freq in khz
LOADC CLK_KHZ_ADDR
LOADI
; divide by 16
SHR
SHR
SHR
SHR
WAIT1LOOP:
INC 0 ; NOP to make loop 16 cycles long
DEC 1
DUP
CBRANCH.NZ WAIT1LOOP
@ -798,7 +810,7 @@ WAIT1LOOP:
%include "sdcardboot.s"
.CPOOL
MESSAGE:
.BYTE 13,10,"ROM Monitor v3.0.3", 13, 10,
.BYTE 13,10,"ROM Monitor v3.1.0", 13, 10,
"Set A)ddress D)eposit eX)amine L)oad G)o B)oot",13,10,0
PROMPT2:
.BYTE "]> ",0