diff --git a/README.md b/README.md
index 3b988ef..0ad4c04 100644
--- a/README.md
+++ b/README.md
@@ -6,8 +6,7 @@ Everything is as simple as possible while still being reasonably useful.
 Everything is open source, so you can read, understand and modify the whole system, hardware and software.
 
 ## Overview
-- homebrew CPU
-- Verilog FPGA SoC
+- homebrew CPU written in Verilog implemented on an FPGA
 - 32-bit word-oriented stack machine architecture
 - running at 83 MHz on an Arty-A7 board with four clocks per instruction
 - has its own instruction set architecture, compatible with nothing
@@ -25,10 +24,13 @@ Everything is open source, so you can read, understand and modify the whole syst
 
 ## Demos
 ### Videos
-- (Video hello world)
-- (Video lines)
 
-### Still Pictures
+|Compiling and Running Hello-World|Moving Lines Demo|
+|---|---|
+|<video src="https://insignificance.de/tridora/tdr-hello.mp4" controls></video>|<video src="https://insignificance.de/tridora/tdr-lines.mp4" controls></video>|
+
+
+### Pictures
 
 |Mandelbrot|Image Viewer|Game of Life|
 |---|---|---|
@@ -71,3 +73,11 @@ Everything is open source, so you can read, understand and modify the whole syst
 - run synthesis, implementation and bitstream generation (Flow -> Generate Bitstream)
 - program your device (Flow -> Open Hardware Manager), the bitstream file should be in **tridoracpu/tridoracpu.runs/impl_1**
 - the bitstream file for (temporarily) programming your device is named **top.bit**, the file for flashing your device is named **top.bin**
+
+## Documentation
+- [Instruction Reference](doc/tridoracpu.md)
+- [Memory Layout](doc/mem.md)
+- [SD-Card controller](doc/spisd.md)
+- [VGA controller](doc/vga.md)
+
+More documentation is coming as time permits.
diff --git a/doc/mem.md b/doc/mem.md
index 10f26c1..fc0f9e8 100644
--- a/doc/mem.md
+++ b/doc/mem.md
@@ -19,8 +19,7 @@ The lower two bits of the address can be viewed as a byte address (0-3) within t
 
 The _BSEL_ and _BPLC_ instructions are designed to assist with accessing bytes within a word.
 
-Because memory is always accessed in words, the CPU is neither big-endian nor little-endian. However, the _BSEL_ and _BPLC_
-instructions are big-endian when accessing bytes within a word, so the system can be considered big-endian.
+The byte ordering is big-endian.
 
 ## Accessing the I/O Area
 The I/O area organizes memory slightly different. Here, pointing out individual bytes is not very useful, so the I/O controllers use register addresses with increments of one. In practice, there is only the VGA framebuffer controller which uses multiple registers.