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rtl/arty-a7/Arty-A7-35-Master.xdc
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rtl/arty-a7/Arty-A7-35-Master.xdc
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## This file is a general .xdc for the Arty A7-35 Rev. D
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## To use it in a project:
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## - uncomment the lines corresponding to used pins
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## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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## Clock signal
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set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]
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create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
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## Switches
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set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports sw0]
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set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports sw1]
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#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
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#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
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## RGB LEDs
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#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
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#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
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#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
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#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
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#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
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#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
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#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
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#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
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#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
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#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
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#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
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#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
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## LEDs
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set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports led0]
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set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports led1]
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set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports led2]
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set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports led3]
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## Buttons
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set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports btn0]
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#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn1 }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
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#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
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#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
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## Pmod Header JA
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set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports sd_cs_n]
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set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports sd_mosi]
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set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports sd_miso]
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set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS33} [get_ports sd_sck]
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#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { sd_dat1 }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
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#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { sd_dat2 }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
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set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports sd_cd]
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#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { sd_nc }]; #IO_25_15 Sch=ja[10]
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###Pmod Header JB
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set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {VGA_R[0]}]
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set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {VGA_R[1]}]
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set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {VGA_R[2]}]
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set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {VGA_R[3]}]
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set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {VGA_B[0]}]
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set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {VGA_B[1]}]
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set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {VGA_B[2]}]
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set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {VGA_B[3]}]
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###Pmod Header JC
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set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {VGA_G[0]}]
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set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {VGA_G[1]}]
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set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {VGA_G[2]}]
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set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {VGA_G[3]}]
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set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports VGA_HS_O]
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set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports VGA_VS_O]
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#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
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#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
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## Pmod Header JD
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#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
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#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
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#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
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#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
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#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
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#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
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#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
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#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
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## USB-UART Interface
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set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports uart_rxd_out]
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set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports uart_txd_in]
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## ChipKit Outer Digital Header
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#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
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#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
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#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
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#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
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#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
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#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
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#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
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#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
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#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
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#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
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#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
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#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
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#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
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#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
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## ChipKit Inner Digital Header
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#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
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#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
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#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
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#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_25_14 Sch=ck_io[29]
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#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_0_14 Sch=ck_io[30]
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#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
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#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
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#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
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#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
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#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
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#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
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#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
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#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
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#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
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#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
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#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
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## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
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## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
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## WARNING: Do not use both sets of constraints at the same time!
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## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
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#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0] ChipKit pin=A0
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#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] ChipKit pin=A0
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#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1
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#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1
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#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2] ChipKit pin=A2
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#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2] ChipKit pin=A2
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#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_n }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3
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#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_p }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3
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#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4] ChipKit pin=A4
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||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4] ChipKit pin=A4
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||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5] ChipKit pin=A5
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||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5] ChipKit pin=A5
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: the following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35 Sch=ck_a[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1] ChipKit pin=A1
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||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2] ChipKit pin=A2
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||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3] ChipKit pin=A3
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||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5] ChipKit pin=A5
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit Analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
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||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
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||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
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||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: the following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { ck_io20 }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { ck_io21 }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { ck_io22 }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { ck_io23 }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { ck_io24 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { ck_io25 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
|
||||
|
||||
## ChipKit SPI
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
|
||||
|
||||
## Misc. ChipKit Ports
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
|
||||
set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports rst]
|
||||
|
||||
## SMSC Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
|
||||
|
||||
## Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Power Measurements
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
|
||||
|
||||
set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
|
||||
48
rtl/arty-a7/Arty_C_mig.ucf
Normal file
48
rtl/arty-a7/Arty_C_mig.ucf
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
NET "ddr3_dq[0]" LOC = "K5" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[1]" LOC = "L3" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[2]" LOC = "K3" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[3]" LOC = "L6" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[4]" LOC = "M3" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[5]" LOC = "M1" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[6]" LOC = "L4" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[7]" LOC = "M2" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[8]" LOC = "V4" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[9]" LOC = "T5" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[10]" LOC = "U4" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[11]" LOC = "V5" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[12]" LOC = "V1" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[13]" LOC = "T3" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[14]" LOC = "U3" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dq[15]" LOC = "R3" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dm[0]" LOC = "L1" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dm[1]" LOC = "U1" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_dqs_p[0]" LOC = "N2" | IOSTANDARD = DIFF_SSTL135 ;
|
||||
NET "ddr3_dqs_n[0]" LOC = "N1" | IOSTANDARD = DIFF_SSTL135 ;
|
||||
NET "ddr3_dqs_p[1]" LOC = "U2" | IOSTANDARD = DIFF_SSTL135 ;
|
||||
NET "ddr3_dqs_n[1]" LOC = "V2" | IOSTANDARD = DIFF_SSTL135 ;
|
||||
NET "ddr3_addr[13]" LOC = "T8" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_addr[12]" LOC = "T6" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_addr[11]" LOC = "U6" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_addr[10]" LOC = "R6" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_addr[9]" LOC = "V7" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_addr[8]" LOC = "R8" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_addr[7]" LOC = "U7" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_addr[6]" LOC = "V6" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_addr[5]" LOC = "R7" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_addr[4]" LOC = "N6" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_addr[3]" LOC = "T1" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_addr[2]" LOC = "N4" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_addr[1]" LOC = "M6" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_addr[0]" LOC = "R2" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_ba[2]" LOC = "P2" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_ba[1]" LOC = "P4" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_ba[0]" LOC = "R1" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_ck_p[0]" LOC = "U9" | IOSTANDARD = DIFF_SSTL135 ;
|
||||
NET "ddr3_ck_n[0]" LOC = "V9" | IOSTANDARD = DIFF_SSTL135 ;
|
||||
NET "ddr3_ras_n" LOC = "P3" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_cas_n" LOC = "M4" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_we_n" LOC = "P5" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_reset_n" LOC = "K6" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_cke[0]" LOC = "N5" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_odt[0]" LOC = "R5" | IOSTANDARD = SSTL135 ;
|
||||
NET "ddr3_cs_n[0]" LOC = "U8" | IOSTANDARD = SSTL135 ;
|
||||
148
rtl/arty-a7/mig_dram_0/mig_a.prj
Normal file
148
rtl/arty-a7/mig_dram_0/mig_a.prj
Normal file
|
|
@ -0,0 +1,148 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project NoOfControllers="1">
|
||||
|
||||
|
||||
|
||||
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
||||
|
||||
<ModuleName>mig_dram_0</ModuleName>
|
||||
|
||||
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||
|
||||
<dci_inputs>1</dci_inputs>
|
||||
|
||||
<Debug_En>OFF</Debug_En>
|
||||
|
||||
<DataDepth_En>1024</DataDepth_En>
|
||||
|
||||
<LowPower_En>ON</LowPower_En>
|
||||
|
||||
<XADC_En>Enabled</XADC_En>
|
||||
|
||||
<TargetFPGA>xc7a35ti-csg324/-1L</TargetFPGA>
|
||||
|
||||
<Version>4.2</Version>
|
||||
|
||||
<SystemClock>No Buffer</SystemClock>
|
||||
|
||||
<ReferenceClock>No Buffer</ReferenceClock>
|
||||
|
||||
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
|
||||
|
||||
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||
|
||||
<InternalVref>1</InternalVref>
|
||||
|
||||
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
|
||||
|
||||
<dci_cascade>0</dci_cascade>
|
||||
|
||||
<Controller number="0">
|
||||
<MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
|
||||
<TimePeriod>3000</TimePeriod>
|
||||
<VccAuxIO>1.8V</VccAuxIO>
|
||||
<PHYRatio>4:1</PHYRatio>
|
||||
<InputClkFreq>83.333</InputClkFreq>
|
||||
<UIExtraClocks>0</UIExtraClocks>
|
||||
<MMCM_VCO>666</MMCM_VCO>
|
||||
<MMCMClkOut0> 1.000</MMCMClkOut0>
|
||||
<MMCMClkOut1>1</MMCMClkOut1>
|
||||
<MMCMClkOut2>1</MMCMClkOut2>
|
||||
<MMCMClkOut3>1</MMCMClkOut3>
|
||||
<MMCMClkOut4>1</MMCMClkOut4>
|
||||
<DataWidth>16</DataWidth>
|
||||
<DeepMemory>1</DeepMemory>
|
||||
<DataMask>1</DataMask>
|
||||
<ECC>Disabled</ECC>
|
||||
<Ordering>Strict</Ordering>
|
||||
<BankMachineCnt>4</BankMachineCnt>
|
||||
<CustomPart>FALSE</CustomPart>
|
||||
<NewPartName/>
|
||||
<RowAddress>14</RowAddress>
|
||||
<ColAddress>10</ColAddress>
|
||||
<BankAddress>3</BankAddress>
|
||||
<MemoryVoltage>1.35V</MemoryVoltage>
|
||||
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
|
||||
<PinSelection>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R2" SLEW="" VCCAUX_IO="" name="ddr3_addr[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" VCCAUX_IO="" name="ddr3_addr[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" VCCAUX_IO="" name="ddr3_addr[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" VCCAUX_IO="" name="ddr3_addr[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T8" SLEW="" VCCAUX_IO="" name="ddr3_addr[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" VCCAUX_IO="" name="ddr3_addr[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" VCCAUX_IO="" name="ddr3_addr[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" VCCAUX_IO="" name="ddr3_addr[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N6" SLEW="" VCCAUX_IO="" name="ddr3_addr[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" VCCAUX_IO="" name="ddr3_addr[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" VCCAUX_IO="" name="ddr3_addr[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" VCCAUX_IO="" name="ddr3_addr[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R8" SLEW="" VCCAUX_IO="" name="ddr3_addr[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" VCCAUX_IO="" name="ddr3_addr[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" VCCAUX_IO="" name="ddr3_ba[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P4" SLEW="" VCCAUX_IO="" name="ddr3_ba[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" VCCAUX_IO="" name="ddr3_ba[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" VCCAUX_IO="" name="ddr3_cas_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="V9" SLEW="" VCCAUX_IO="" name="ddr3_ck_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="U9" SLEW="" VCCAUX_IO="" name="ddr3_ck_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" VCCAUX_IO="" name="ddr3_cke[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U8" SLEW="" VCCAUX_IO="" name="ddr3_cs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L1" SLEW="" VCCAUX_IO="" name="ddr3_dm[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" VCCAUX_IO="" name="ddr3_dm[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K5" SLEW="" VCCAUX_IO="" name="ddr3_dq[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U4" SLEW="" VCCAUX_IO="" name="ddr3_dq[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" VCCAUX_IO="" name="ddr3_dq[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V1" SLEW="" VCCAUX_IO="" name="ddr3_dq[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" VCCAUX_IO="" name="ddr3_dq[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" VCCAUX_IO="" name="ddr3_dq[14]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" VCCAUX_IO="" name="ddr3_dq[15]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L3" SLEW="" VCCAUX_IO="" name="ddr3_dq[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" VCCAUX_IO="" name="ddr3_dq[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" VCCAUX_IO="" name="ddr3_dq[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" VCCAUX_IO="" name="ddr3_dq[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" VCCAUX_IO="" name="ddr3_dq[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" VCCAUX_IO="" name="ddr3_dq[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" VCCAUX_IO="" name="ddr3_dq[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" VCCAUX_IO="" name="ddr3_dq[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" VCCAUX_IO="" name="ddr3_dq[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="N1" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="V2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="U2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R5" SLEW="" VCCAUX_IO="" name="ddr3_odt[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P3" SLEW="" VCCAUX_IO="" name="ddr3_ras_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" VCCAUX_IO="" name="ddr3_reset_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" VCCAUX_IO="" name="ddr3_we_n"/>
|
||||
</PinSelection>
|
||||
<System_Control>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
|
||||
</System_Control>
|
||||
<TimingParameters>
|
||||
<Parameters tcke="5.625" tfaw="45" tras="36" trcd="13.5" trefi="7.8" trfc="160" trp="13.5" trrd="7.5" trtp="7.5" twtr="7.5"/>
|
||||
</TimingParameters>
|
||||
<mrBurstLength name="Burst Length">8 - Fixed</mrBurstLength>
|
||||
<mrBurstType name="Read Burst Type and Length">Sequential</mrBurstType>
|
||||
<mrCasLatency name="CAS Latency">5</mrCasLatency>
|
||||
<mrMode name="Mode">Normal</mrMode>
|
||||
<mrDllReset name="DLL Reset">No</mrDllReset>
|
||||
<mrPdMode name="DLL control for precharge PD">Slow Exit</mrPdMode>
|
||||
<emrDllEnable name="DLL Enable">Enable</emrDllEnable>
|
||||
<emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/6</emrOutputDriveStrength>
|
||||
<emrMirrorSelection name="Address Mirroring">Disable</emrMirrorSelection>
|
||||
<emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
|
||||
<emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/6</emrRTT>
|
||||
<emrPosted name="Additive Latency (AL)">0</emrPosted>
|
||||
<emrOCD name="Write Leveling Enable">Disabled</emrOCD>
|
||||
<emrDQS name="TDQS enable">Enabled</emrDQS>
|
||||
<emrRDQS name="Qoff">Output Buffer Enabled</emrRDQS>
|
||||
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh">Full Array</mr2PartialArraySelfRefresh>
|
||||
<mr2CasWriteLatency name="CAS write latency">5</mr2CasWriteLatency>
|
||||
<mr2AutoSelfRefresh name="Auto Self Refresh">Enabled</mr2AutoSelfRefresh>
|
||||
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate">Normal</mr2SelfRefreshTempRange>
|
||||
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)">Dynamic ODT off</mr2RTTWR>
|
||||
<PortInterface>NATIVE</PortInterface>
|
||||
</Controller>
|
||||
|
||||
|
||||
</Project>
|
||||
148
rtl/arty-a7/mig_dram_0/mig_b.prj
Normal file
148
rtl/arty-a7/mig_dram_0/mig_b.prj
Normal file
|
|
@ -0,0 +1,148 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project NoOfControllers="1">
|
||||
|
||||
|
||||
|
||||
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
||||
|
||||
<ModuleName>mig_dram_0</ModuleName>
|
||||
|
||||
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||
|
||||
<dci_inputs>1</dci_inputs>
|
||||
|
||||
<Debug_En>OFF</Debug_En>
|
||||
|
||||
<DataDepth_En>1024</DataDepth_En>
|
||||
|
||||
<LowPower_En>ON</LowPower_En>
|
||||
|
||||
<XADC_En>Enabled</XADC_En>
|
||||
|
||||
<TargetFPGA>xc7a35ti-csg324/-1L</TargetFPGA>
|
||||
|
||||
<Version>4.2</Version>
|
||||
|
||||
<SystemClock>No Buffer</SystemClock>
|
||||
|
||||
<ReferenceClock>No Buffer</ReferenceClock>
|
||||
|
||||
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
|
||||
|
||||
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||
|
||||
<InternalVref>1</InternalVref>
|
||||
|
||||
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
|
||||
|
||||
<dci_cascade>0</dci_cascade>
|
||||
|
||||
<Controller number="0">
|
||||
<MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
|
||||
<TimePeriod>3000</TimePeriod>
|
||||
<VccAuxIO>1.8V</VccAuxIO>
|
||||
<PHYRatio>4:1</PHYRatio>
|
||||
<InputClkFreq>83.333</InputClkFreq>
|
||||
<UIExtraClocks>0</UIExtraClocks>
|
||||
<MMCM_VCO>666</MMCM_VCO>
|
||||
<MMCMClkOut0> 1.000</MMCMClkOut0>
|
||||
<MMCMClkOut1>1</MMCMClkOut1>
|
||||
<MMCMClkOut2>1</MMCMClkOut2>
|
||||
<MMCMClkOut3>1</MMCMClkOut3>
|
||||
<MMCMClkOut4>1</MMCMClkOut4>
|
||||
<DataWidth>16</DataWidth>
|
||||
<DeepMemory>1</DeepMemory>
|
||||
<DataMask>1</DataMask>
|
||||
<ECC>Disabled</ECC>
|
||||
<Ordering>Strict</Ordering>
|
||||
<BankMachineCnt>4</BankMachineCnt>
|
||||
<CustomPart>FALSE</CustomPart>
|
||||
<NewPartName/>
|
||||
<RowAddress>14</RowAddress>
|
||||
<ColAddress>10</ColAddress>
|
||||
<BankAddress>3</BankAddress>
|
||||
<MemoryVoltage>1.35V</MemoryVoltage>
|
||||
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
|
||||
<PinSelection>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R2" SLEW="" VCCAUX_IO="" name="ddr3_addr[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" VCCAUX_IO="" name="ddr3_addr[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" VCCAUX_IO="" name="ddr3_addr[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" VCCAUX_IO="" name="ddr3_addr[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T8" SLEW="" VCCAUX_IO="" name="ddr3_addr[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" VCCAUX_IO="" name="ddr3_addr[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" VCCAUX_IO="" name="ddr3_addr[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" VCCAUX_IO="" name="ddr3_addr[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N6" SLEW="" VCCAUX_IO="" name="ddr3_addr[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" VCCAUX_IO="" name="ddr3_addr[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" VCCAUX_IO="" name="ddr3_addr[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" VCCAUX_IO="" name="ddr3_addr[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R8" SLEW="" VCCAUX_IO="" name="ddr3_addr[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" VCCAUX_IO="" name="ddr3_addr[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" VCCAUX_IO="" name="ddr3_ba[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P4" SLEW="" VCCAUX_IO="" name="ddr3_ba[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" VCCAUX_IO="" name="ddr3_ba[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" VCCAUX_IO="" name="ddr3_cas_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="V9" SLEW="" VCCAUX_IO="" name="ddr3_ck_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="U9" SLEW="" VCCAUX_IO="" name="ddr3_ck_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" VCCAUX_IO="" name="ddr3_cke[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U8" SLEW="" VCCAUX_IO="" name="ddr3_cs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L1" SLEW="" VCCAUX_IO="" name="ddr3_dm[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" VCCAUX_IO="" name="ddr3_dm[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K5" SLEW="" VCCAUX_IO="" name="ddr3_dq[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U4" SLEW="" VCCAUX_IO="" name="ddr3_dq[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" VCCAUX_IO="" name="ddr3_dq[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V1" SLEW="" VCCAUX_IO="" name="ddr3_dq[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" VCCAUX_IO="" name="ddr3_dq[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" VCCAUX_IO="" name="ddr3_dq[14]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" VCCAUX_IO="" name="ddr3_dq[15]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L3" SLEW="" VCCAUX_IO="" name="ddr3_dq[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" VCCAUX_IO="" name="ddr3_dq[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" VCCAUX_IO="" name="ddr3_dq[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" VCCAUX_IO="" name="ddr3_dq[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" VCCAUX_IO="" name="ddr3_dq[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" VCCAUX_IO="" name="ddr3_dq[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" VCCAUX_IO="" name="ddr3_dq[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" VCCAUX_IO="" name="ddr3_dq[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" VCCAUX_IO="" name="ddr3_dq[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="N1" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="V2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="U2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R5" SLEW="" VCCAUX_IO="" name="ddr3_odt[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P3" SLEW="" VCCAUX_IO="" name="ddr3_ras_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" VCCAUX_IO="" name="ddr3_reset_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" VCCAUX_IO="" name="ddr3_we_n"/>
|
||||
</PinSelection>
|
||||
<System_Control>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
|
||||
</System_Control>
|
||||
<TimingParameters>
|
||||
<Parameters tcke="5.625" tfaw="45" tras="36" trcd="13.5" trefi="7.8" trfc="160" trp="13.5" trrd="7.5" trtp="7.5" twtr="7.5"/>
|
||||
</TimingParameters>
|
||||
<mrBurstLength name="Burst Length">8 - Fixed</mrBurstLength>
|
||||
<mrBurstType name="Read Burst Type and Length">Sequential</mrBurstType>
|
||||
<mrCasLatency name="CAS Latency">5</mrCasLatency>
|
||||
<mrMode name="Mode">Normal</mrMode>
|
||||
<mrDllReset name="DLL Reset">No</mrDllReset>
|
||||
<mrPdMode name="DLL control for precharge PD">Slow Exit</mrPdMode>
|
||||
<emrDllEnable name="DLL Enable">Enable</emrDllEnable>
|
||||
<emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/6</emrOutputDriveStrength>
|
||||
<emrMirrorSelection name="Address Mirroring">Disable</emrMirrorSelection>
|
||||
<emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
|
||||
<emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/6</emrRTT>
|
||||
<emrPosted name="Additive Latency (AL)">0</emrPosted>
|
||||
<emrOCD name="Write Leveling Enable">Disabled</emrOCD>
|
||||
<emrDQS name="TDQS enable">Enabled</emrDQS>
|
||||
<emrRDQS name="Qoff">Output Buffer Enabled</emrRDQS>
|
||||
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh">Full Array</mr2PartialArraySelfRefresh>
|
||||
<mr2CasWriteLatency name="CAS write latency">5</mr2CasWriteLatency>
|
||||
<mr2AutoSelfRefresh name="Auto Self Refresh">Enabled</mr2AutoSelfRefresh>
|
||||
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate">Normal</mr2SelfRefreshTempRange>
|
||||
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)">Dynamic ODT off</mr2RTTWR>
|
||||
<PortInterface>NATIVE</PortInterface>
|
||||
</Controller>
|
||||
|
||||
|
||||
</Project>
|
||||
176
rtl/arty-a7/sdspi_testbench_behav.wcfg
Normal file
176
rtl/arty-a7/sdspi_testbench_behav.wcfg
Normal file
|
|
@ -0,0 +1,176 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="sdspi_testbench_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="glbl" />
|
||||
<top_module name="sdspi_testbench" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="35023635fs"></ZoomStartTime>
|
||||
<ZoomEndTime time="36066046fs"></ZoomEndTime>
|
||||
<Cursor1Time time="32155000fs"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="149"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="90"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="35" />
|
||||
<wave_markers>
|
||||
<marker time="30925000" label="" />
|
||||
</wave_markers>
|
||||
<wvobject fp_name="/sdspi_testbench/clk" type="logic">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/tx_data" type="array">
|
||||
<obj_property name="ElementShortName">tx_data[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">tx_data[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/rx_data" type="array">
|
||||
<obj_property name="ElementShortName">rx_data[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">rx_data[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/rx_shifter" type="array">
|
||||
<obj_property name="ElementShortName">rx_shifter[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">rx_shifter[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/tx_shifter" type="array">
|
||||
<obj_property name="ElementShortName">tx_shifter[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">tx_shifter[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/tx_fifo_out" type="array">
|
||||
<obj_property name="ElementShortName">tx_fifo_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">tx_fifo_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/tx_fifo_rd_en" type="logic">
|
||||
<obj_property name="ElementShortName">tx_fifo_rd_en</obj_property>
|
||||
<obj_property name="ObjectShortName">tx_fifo_rd_en</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/tx_fifo_wr_en" type="logic">
|
||||
<obj_property name="ElementShortName">tx_fifo_wr_en</obj_property>
|
||||
<obj_property name="ObjectShortName">tx_fifo_wr_en</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/rx_fifo_wr_en" type="logic">
|
||||
<obj_property name="ElementShortName">rx_fifo_wr_en</obj_property>
|
||||
<obj_property name="ObjectShortName">rx_fifo_wr_en</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/rx_bit_recvd" type="logic">
|
||||
<obj_property name="ElementShortName">rx_bit_recvd</obj_property>
|
||||
<obj_property name="ObjectShortName">rx_bit_recvd</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/tx_fifo/tail_x" type="array">
|
||||
<obj_property name="ElementShortName">tail_x[4:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">tail_x[4:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/tx_fifo/head_x" type="array">
|
||||
<obj_property name="ElementShortName">head_x[4:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">head_x[4:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/tx_ready" type="logic">
|
||||
<obj_property name="ElementShortName">tx_ready</obj_property>
|
||||
<obj_property name="ObjectShortName">tx_ready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/tx_empty" type="logic">
|
||||
<obj_property name="ElementShortName">tx_empty</obj_property>
|
||||
<obj_property name="ObjectShortName">tx_empty</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/rx_avail" type="logic">
|
||||
<obj_property name="ElementShortName">rx_avail</obj_property>
|
||||
<obj_property name="ObjectShortName">rx_avail</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/tx_write" type="logic">
|
||||
<obj_property name="ElementShortName">tx_write</obj_property>
|
||||
<obj_property name="ObjectShortName">tx_write</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/rx_read" type="logic">
|
||||
<obj_property name="ElementShortName">rx_read</obj_property>
|
||||
<obj_property name="ObjectShortName">rx_read</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/ctrl_write" type="logic">
|
||||
<obj_property name="ElementShortName">ctrl_write</obj_property>
|
||||
<obj_property name="ObjectShortName">ctrl_write</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/rx_filter_en" type="logic">
|
||||
<obj_property name="ElementShortName">rx_filter_en</obj_property>
|
||||
<obj_property name="ObjectShortName">rx_filter_en</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/txrx_en" type="logic">
|
||||
<obj_property name="ElementShortName">txrx_en</obj_property>
|
||||
<obj_property name="ObjectShortName">txrx_en</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/spiclk_div_wr" type="logic">
|
||||
<obj_property name="ElementShortName">spiclk_div_wr</obj_property>
|
||||
<obj_property name="ObjectShortName">spiclk_div_wr</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/spi_clk_on" type="logic">
|
||||
<obj_property name="ElementShortName">spi_clk_on</obj_property>
|
||||
<obj_property name="ObjectShortName">spi_clk_on</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/spiclk_f_en" type="logic">
|
||||
<obj_property name="ElementShortName">spiclk_f_en</obj_property>
|
||||
<obj_property name="ObjectShortName">spiclk_f_en</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/spi_clk_f_on" type="logic">
|
||||
<obj_property name="ElementShortName">spi_clk_f_on</obj_property>
|
||||
<obj_property name="ObjectShortName">spi_clk_f_on</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/sd_cs_n" type="logic">
|
||||
<obj_property name="ElementShortName">sd_cs_n</obj_property>
|
||||
<obj_property name="ObjectShortName">sd_cs_n</obj_property>
|
||||
<obj_property name="CustomSignalColor">#DCDCDC</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/sd_mosi" type="logic">
|
||||
<obj_property name="ElementShortName">sd_mosi</obj_property>
|
||||
<obj_property name="ObjectShortName">sd_mosi</obj_property>
|
||||
<obj_property name="CustomSignalColor">#00FFFF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/sd_miso" type="logic">
|
||||
<obj_property name="ElementShortName">sd_miso</obj_property>
|
||||
<obj_property name="ObjectShortName">sd_miso</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/sd_sck" type="logic">
|
||||
<obj_property name="ElementShortName">sd_sck</obj_property>
|
||||
<obj_property name="ObjectShortName">sd_sck</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFFF00</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/xcvr_on" type="logic">
|
||||
<obj_property name="ElementShortName">xcvr_on</obj_property>
|
||||
<obj_property name="ObjectShortName">xcvr_on</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/hphase_start" type="logic">
|
||||
<obj_property name="ElementShortName">hphase_start</obj_property>
|
||||
<obj_property name="ObjectShortName">hphase_start</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/clk_phase" type="array">
|
||||
<obj_property name="ElementShortName">clk_phase[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">clk_phase[1:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#D2691E</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/running" type="logic">
|
||||
<obj_property name="ElementShortName">running</obj_property>
|
||||
<obj_property name="ObjectShortName">running</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/xcvr_bitcount" type="array">
|
||||
<obj_property name="ElementShortName">xcvr_bitcount[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">xcvr_bitcount[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/spi_clk_count" type="array">
|
||||
<obj_property name="ElementShortName">spi_clk_count[6:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">spi_clk_count[6:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/sdspi_testbench/UUT/spi_clk_div" type="array">
|
||||
<obj_property name="ElementShortName">spi_clk_div[6:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">spi_clk_div[6:0]</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
88
rtl/arty-a7/testbench_behav1.wcfg
Normal file
88
rtl/arty-a7/testbench_behav1.wcfg
Normal file
|
|
@ -0,0 +1,88 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="testbench_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="glbl" />
|
||||
<top_module name="testbench" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="3880386400fs"></ZoomStartTime>
|
||||
<ZoomEndTime time="4023922720fs"></ZoomEndTime>
|
||||
<Cursor1Time time="4000000000fs"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="209"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="90"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="16" />
|
||||
<wvobject fp_name="/testbench/clk" type="logic">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/addr" type="array">
|
||||
<obj_property name="ElementShortName">addr[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">addr[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/data_in" type="array">
|
||||
<obj_property name="ElementShortName">data_in[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">data_in[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/data_out" type="array">
|
||||
<obj_property name="ElementShortName">data_out[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">data_out[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/seq_state" type="array">
|
||||
<obj_property name="ElementShortName">seq_state[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">seq_state[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/PC" type="array">
|
||||
<obj_property name="ElementShortName">PC[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">PC[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/nPC" type="array">
|
||||
<obj_property name="ElementShortName">nPC[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">nPC[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/ins" type="array">
|
||||
<obj_property name="ElementShortName">ins[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">ins[15:0]</obj_property>
|
||||
<obj_property name="Radix">BINARYRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/ins_branch" type="logic">
|
||||
<obj_property name="ElementShortName">ins_branch</obj_property>
|
||||
<obj_property name="ObjectShortName">ins_branch</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/ins_loadrel" type="logic">
|
||||
<obj_property name="ElementShortName">ins_loadrel</obj_property>
|
||||
<obj_property name="ObjectShortName">ins_loadrel</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/X" type="array">
|
||||
<obj_property name="ElementShortName">X[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">X[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/nX" type="array">
|
||||
<obj_property name="ElementShortName">nX[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">nX[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/FP" type="array">
|
||||
<obj_property name="ElementShortName">FP[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">FP[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/pc_next_ins" type="array">
|
||||
<obj_property name="ElementShortName">pc_next_ins[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">pc_next_ins[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/mem_wait" type="logic">
|
||||
<obj_property name="ElementShortName">mem_wait</obj_property>
|
||||
<obj_property name="ObjectShortName">mem_wait</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/testbench/top0/cpu0/ins_buf" type="array">
|
||||
<obj_property name="ElementShortName">ins_buf[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">ins_buf[15:0]</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
683
rtl/arty-a7/tridoracpu.tcl
Normal file
683
rtl/arty-a7/tridoracpu.tcl
Normal file
|
|
@ -0,0 +1,683 @@
|
|||
#*****************************************************************************************
|
||||
# Vivado (TM) v2020.1 (64-bit)
|
||||
#
|
||||
# tridoracpu.tcl: Tcl script for re-creating project 'tridoracpu'
|
||||
#
|
||||
# Generated by Vivado on Sat Sep 14 23:58:12 +0200 2024
|
||||
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
|
||||
#
|
||||
# This file contains the Vivado Tcl commands for re-creating the project to the state*
|
||||
# when this script was generated. In order to re-create the project, please source this
|
||||
# file in the Vivado Tcl Shell.
|
||||
#
|
||||
# * Note that the runs in the created project will be configured the same way as the
|
||||
# original project, however they will not be launched automatically. To regenerate the
|
||||
# run results please launch the synthesis/implementation runs as needed.
|
||||
#
|
||||
#*****************************************************************************************
|
||||
|
||||
# uncomment next two statements if you have never initialized the Xilinx Board Store
|
||||
# this will take quite some time
|
||||
#xhub::refresh_catalog [xhub::get_xstores xilinx_board_store]
|
||||
#xhub::install [xhub::get_xitems]
|
||||
|
||||
# Set the reference directory for source file relative paths
|
||||
set origin_dir "change_this_to_your_rtl_directory"
|
||||
|
||||
set xilinx_board_store_dir [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]
|
||||
set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]
|
||||
|
||||
# Use origin directory path location variable, if specified in the tcl shell
|
||||
if { [info exists ::origin_dir_loc] } {
|
||||
set origin_dir $::origin_dir_loc
|
||||
}
|
||||
|
||||
# Set the project name
|
||||
set _xil_proj_name_ "tridoracpu"
|
||||
|
||||
# Use project name variable, if specified in the tcl shell
|
||||
if { [info exists ::user_project_name] } {
|
||||
set _xil_proj_name_ $::user_project_name
|
||||
}
|
||||
|
||||
variable script_file
|
||||
set script_file "tridoracpu.tcl"
|
||||
|
||||
# Help information for this script
|
||||
proc print_help {} {
|
||||
variable script_file
|
||||
puts "\nDescription:"
|
||||
puts "Recreate a Vivado project from this script. The created project will be"
|
||||
puts "functionally equivalent to the original project for which this script was"
|
||||
puts "generated. The script contains commands for creating a project, filesets,"
|
||||
puts "runs, adding/importing sources and setting properties on various objects.\n"
|
||||
puts "Syntax:"
|
||||
puts "$script_file"
|
||||
puts "$script_file -tclargs \[--origin_dir <path>\]"
|
||||
puts "$script_file -tclargs \[--project_name <name>\]"
|
||||
puts "$script_file -tclargs \[--help\]\n"
|
||||
puts "Usage:"
|
||||
puts "Name Description"
|
||||
puts "-------------------------------------------------------------------------"
|
||||
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
|
||||
puts " origin_dir path value is \".\", otherwise, the value"
|
||||
puts " that was set with the \"-paths_relative_to\" switch"
|
||||
puts " when this script was generated.\n"
|
||||
puts "\[--project_name <name>\] Create project with the specified name. Default"
|
||||
puts " name is the name of the project from where this"
|
||||
puts " script was generated.\n"
|
||||
puts "\[--help\] Print help information for this script"
|
||||
puts "-------------------------------------------------------------------------\n"
|
||||
exit 0
|
||||
}
|
||||
|
||||
if { $::argc > 0 } {
|
||||
for {set i 0} {$i < $::argc} {incr i} {
|
||||
set option [string trim [lindex $::argv $i]]
|
||||
switch -regexp -- $option {
|
||||
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
|
||||
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
|
||||
"--help" { print_help }
|
||||
default {
|
||||
if { [regexp {^-} $option] } {
|
||||
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
|
||||
return 1
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Set the directory path for the original project from where this script was exported
|
||||
set orig_proj_dir "[file normalize "${origin_dir}/arty-a7"]"
|
||||
|
||||
# Create project
|
||||
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a35ticsg324-1L
|
||||
|
||||
# Set the directory path for the new project
|
||||
set proj_dir [get_property directory [current_project]]
|
||||
|
||||
# Set project properties
|
||||
set obj [current_project]
|
||||
#set_property -name "board_part_repo_paths" -value "[file normalize "$xilinx_board_store_dir"]" -objects $obj
|
||||
set_property -name "board_part" -value "digilentinc.com:arty-a7-35:part0:1.0" -objects $obj
|
||||
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
|
||||
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
|
||||
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
|
||||
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
|
||||
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
|
||||
set_property -name "platform.board_id" -value "arty-a7-35" -objects $obj
|
||||
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
|
||||
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
|
||||
set_property -name "simulator_language" -value "Mixed" -objects $obj
|
||||
set_property -name "source_mgmt_mode" -value "DisplayOnly" -objects $obj
|
||||
set_property -name "webtalk.activehdl_export_sim" -value "4" -objects $obj
|
||||
set_property -name "webtalk.ies_export_sim" -value "4" -objects $obj
|
||||
set_property -name "webtalk.modelsim_export_sim" -value "4" -objects $obj
|
||||
set_property -name "webtalk.questa_export_sim" -value "4" -objects $obj
|
||||
set_property -name "webtalk.riviera_export_sim" -value "4" -objects $obj
|
||||
set_property -name "webtalk.vcs_export_sim" -value "4" -objects $obj
|
||||
set_property -name "webtalk.xsim_export_sim" -value "4" -objects $obj
|
||||
set_property -name "webtalk.xsim_launch_sim" -value "537" -objects $obj
|
||||
|
||||
# Create 'sources_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet sources_1] ""]} {
|
||||
create_fileset -srcset sources_1
|
||||
}
|
||||
|
||||
# Set 'sources_1' fileset object
|
||||
set obj [get_filesets sources_1]
|
||||
set files [list \
|
||||
[file normalize "${origin_dir}/src/uart.v"] \
|
||||
]
|
||||
add_files -norecurse -fileset $obj $files
|
||||
|
||||
# Add local files from the original project (-no_copy_sources specified)
|
||||
set files [list \
|
||||
[file normalize "${origin_dir}/src/cpuclk.v" ]\
|
||||
[file normalize "${origin_dir}/src/display_clock.v" ]\
|
||||
[file normalize "${origin_dir}/src/mem.v" ]\
|
||||
[file normalize "${origin_dir}/src/stack.v" ]\
|
||||
[file normalize "${origin_dir}/src/stackcpu.v" ]\
|
||||
[file normalize "${origin_dir}/src/vgafb.v" ]\
|
||||
[file normalize "${origin_dir}/src/top.v" ]\
|
||||
[file normalize "${origin_dir}/src/testbench.v" ]\
|
||||
[file normalize "${orig_proj_dir}/rom.mem" ]\
|
||||
[file normalize "${orig_proj_dir}/mig_dram_0/mig_a.prj" ]\
|
||||
[file normalize "${orig_proj_dir}/mig_dram_0/mig_b.prj" ]\
|
||||
[file normalize "${origin_dir}/src/dram_bridge.v" ]\
|
||||
[file normalize "${origin_dir}/src/sdspi.v" ]\
|
||||
[file normalize "${origin_dir}/src/bram_tdp.v" ]\
|
||||
[file normalize "${origin_dir}/src/palette.v" ]\
|
||||
[file normalize "${origin_dir}/src/irqctrl.v" ]\
|
||||
[file normalize "${origin_dir}/src/fifo.v" ]\
|
||||
[file normalize "${origin_dir}/src/fifo_testbench.v" ]\
|
||||
[file normalize "${origin_dir}/src/sdspi_testbench.v" ]\
|
||||
]
|
||||
set added_files [add_files -fileset sources_1 $files]
|
||||
|
||||
# Set 'sources_1' fileset file properties for remote files
|
||||
set file "$origin_dir/src/uart.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
|
||||
|
||||
# Set 'sources_1' fileset file properties for local files
|
||||
set file "src/cpuclk.v"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
|
||||
set file "src/display_clock.v"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "is_enabled" -value "0" -objects $file_obj
|
||||
|
||||
set file "src/mem.v"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
|
||||
set file "src/stack.v"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
|
||||
set file "src/stackcpu.v"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
|
||||
set file "src/vgafb.v"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
|
||||
set file "src/top.v"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
|
||||
set file "src/testbench.v"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "used_in" -value "" -objects $file_obj
|
||||
set_property -name "used_in_implementation" -value "0" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
set_property -name "used_in_synthesis" -value "0" -objects $file_obj
|
||||
|
||||
set file "arty-a7/rom.mem"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "Memory File" -objects $file_obj
|
||||
|
||||
set file "arty-a7/mig_dram_0/mig_a.prj"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "scoped_to_cells" -value "mig_dram_0" -objects $file_obj
|
||||
|
||||
set file "arty-a7/mig_dram_0/mig_b.prj"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "scoped_to_cells" -value "mig_dram_0" -objects $file_obj
|
||||
|
||||
set file "src/dram_bridge.v"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
|
||||
set file "src/palette.v"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
|
||||
set file "src/irqctrl.v"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
|
||||
set file "src/fifo_testbench.v"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "used_in" -value "" -objects $file_obj
|
||||
set_property -name "used_in_implementation" -value "0" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
set_property -name "used_in_synthesis" -value "0" -objects $file_obj
|
||||
|
||||
|
||||
# Set 'sources_1' fileset properties
|
||||
set obj [get_filesets sources_1]
|
||||
set_property -name "top" -value "top" -objects $obj
|
||||
set_property -name "top_auto_set" -value "0" -objects $obj
|
||||
|
||||
# Set 'sources_1' fileset object
|
||||
set obj [get_filesets sources_1]
|
||||
# Add local files from the original project (-no_copy_sources specified)
|
||||
set files [list \
|
||||
[file normalize "${orig_proj_dir}/mig_dram_0/mig_dram_0.xci" ]\
|
||||
]
|
||||
set added_files [add_files -fileset sources_1 $files]
|
||||
|
||||
# Set 'sources_1' fileset file properties for remote files
|
||||
# None
|
||||
|
||||
# Set 'sources_1' fileset file properties for local files
|
||||
set file "arty-a7/mig_dram_0/mig_dram_0.xci"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
||||
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
||||
if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
|
||||
|
||||
# Create 'constrs_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet constrs_1] ""]} {
|
||||
create_fileset -constrset constrs_1
|
||||
}
|
||||
|
||||
# Set 'constrs_1' fileset object
|
||||
set obj [get_filesets constrs_1]
|
||||
|
||||
# Add/Import constrs file and set constrs file properties
|
||||
set file "[file normalize ${origin_dir}/arty-a7/Arty-A7-35-Master.xdc]"
|
||||
set file_added [add_files -norecurse -fileset $obj [list $file]]
|
||||
set file "$origin_dir/arty-a7/Arty-A7-35-Master.xdc"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "XDC" -objects $file_obj
|
||||
|
||||
# Set 'constrs_1' fileset properties
|
||||
set obj [get_filesets constrs_1]
|
||||
set_property -name "target_constrs_file" -value "$orig_proj_dir/Arty-A7-35-Master.xdc" -objects $obj
|
||||
set_property -name "target_ucf" -value "$orig_proj_dir/Arty-A7-35-Master.xdc" -objects $obj
|
||||
|
||||
# Create 'sim_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet sim_1] ""]} {
|
||||
create_fileset -simset sim_1
|
||||
}
|
||||
|
||||
# Set 'sim_1' fileset object
|
||||
set obj [get_filesets sim_1]
|
||||
# Add local files from the original project (-no_copy_sources specified)
|
||||
set files [list \
|
||||
[file normalize "${origin_dir}/src/uart_tb.v" ]\
|
||||
[file normalize "${orig_proj_dir}/testbench_behav1.wcfg" ]\
|
||||
]
|
||||
set added_files [add_files -fileset sim_1 $files]
|
||||
|
||||
# Set 'sim_1' fileset file properties for remote files
|
||||
# None
|
||||
|
||||
# Set 'sim_1' fileset file properties for local files
|
||||
set file [file normalize "${origin_dir}/src/uart_tb.v"]
|
||||
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
|
||||
set_property -name "used_in" -value "" -objects $file_obj
|
||||
set_property -name "used_in_implementation" -value "0" -objects $file_obj
|
||||
set_property -name "used_in_simulation" -value "0" -objects $file_obj
|
||||
set_property -name "used_in_synthesis" -value "0" -objects $file_obj
|
||||
|
||||
|
||||
# Set 'sim_1' fileset properties
|
||||
set obj [get_filesets sim_1]
|
||||
set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
|
||||
set_property -name "nl.mode" -value "funcsim" -objects $obj
|
||||
set_property -name "top" -value "testbench" -objects $obj
|
||||
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
|
||||
|
||||
# Create 'sim_fifo' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet sim_fifo] ""]} {
|
||||
create_fileset -simset sim_fifo
|
||||
}
|
||||
|
||||
# Set 'sim_fifo' fileset object
|
||||
set obj [get_filesets sim_fifo]
|
||||
# Add local files from the original project (-no_copy_sources specified)
|
||||
set files [list \
|
||||
[file normalize "${origin_dir}/src/fifo.v" ]\
|
||||
[file normalize "${origin_dir}/src/fifo_testbench.v" ]\
|
||||
]
|
||||
set added_files [add_files -fileset sim_fifo $files]
|
||||
|
||||
# Set 'sim_fifo' fileset file properties for remote files
|
||||
# None
|
||||
|
||||
# Set 'sim_fifo' fileset file properties for local files
|
||||
# None
|
||||
|
||||
# Set 'sim_fifo' fileset properties
|
||||
set obj [get_filesets sim_fifo]
|
||||
set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
|
||||
set_property -name "top" -value "fifo_testbench" -objects $obj
|
||||
set_property -name "top_auto_set" -value "0" -objects $obj
|
||||
|
||||
# Create 'sim_sdspi' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet sim_sdspi] ""]} {
|
||||
create_fileset -simset sim_sdspi
|
||||
}
|
||||
|
||||
# Set 'sim_sdspi' fileset object
|
||||
set obj [get_filesets sim_sdspi]
|
||||
# Add local files from the original project (-no_copy_sources specified)
|
||||
set files [list \
|
||||
[file normalize "${orig_proj_dir}/sdspi_testbench_behav.wcfg" ]\
|
||||
]
|
||||
set added_files [add_files -fileset sim_sdspi $files]
|
||||
|
||||
# Set 'sim_sdspi' fileset file properties for remote files
|
||||
# None
|
||||
|
||||
# Set 'sim_sdspi' fileset file properties for local files
|
||||
# None
|
||||
|
||||
# Set 'sim_sdspi' fileset properties
|
||||
set obj [get_filesets sim_sdspi]
|
||||
set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
|
||||
set_property -name "sim_mode" -value "post-synthesis" -objects $obj
|
||||
set_property -name "top" -value "sdspi_testbench" -objects $obj
|
||||
set_property -name "top_auto_set" -value "0" -objects $obj
|
||||
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
|
||||
set_property -name "xsim.simulate.runtime" -value "10ms" -objects $obj
|
||||
|
||||
# Set 'utils_1' fileset object
|
||||
set obj [get_filesets utils_1]
|
||||
# Empty (no sources present)
|
||||
|
||||
# Set 'utils_1' fileset properties
|
||||
set obj [get_filesets utils_1]
|
||||
|
||||
# Create 'synth_1' run (if not found)
|
||||
if {[string equal [get_runs -quiet synth_1] ""]} {
|
||||
create_run -name synth_1 -part xc7a35ticsg324-1L -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
|
||||
} else {
|
||||
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
|
||||
set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
|
||||
}
|
||||
set obj [get_runs synth_1]
|
||||
set_property set_report_strategy_name 1 $obj
|
||||
set_property report_strategy {Vivado Synthesis Default Reports} $obj
|
||||
set_property set_report_strategy_name 0 $obj
|
||||
# Create 'synth_1_synth_report_utilization_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
|
||||
create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
set obj [get_runs synth_1]
|
||||
set_property -name "needs_refresh" -value "1" -objects $obj
|
||||
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
|
||||
|
||||
# set the current synth run
|
||||
current_run -synthesis [get_runs synth_1]
|
||||
|
||||
# Create 'impl_1' run (if not found)
|
||||
if {[string equal [get_runs -quiet impl_1] ""]} {
|
||||
create_run -name impl_1 -part xc7a35ticsg324-1L -flow {Vivado Implementation 2020} -strategy "Performance_RefinePlacement" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
|
||||
} else {
|
||||
set_property strategy "Performance_RefinePlacement" [get_runs impl_1]
|
||||
set_property flow "Vivado Implementation 2020" [get_runs impl_1]
|
||||
}
|
||||
set obj [get_runs impl_1]
|
||||
set_property set_report_strategy_name 1 $obj
|
||||
set_property report_strategy {Vivado Implementation Default Reports} $obj
|
||||
set_property set_report_strategy_name 0 $obj
|
||||
# Create 'impl_1_init_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_opt_report_drc_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
|
||||
create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_io_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_utilization_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_control_sets_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "options.verbose" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_drc_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_methodology_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_power_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_route_status_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_bus_skew_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
|
||||
create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
set obj [get_runs impl_1]
|
||||
set_property -name "needs_refresh" -value "1" -objects $obj
|
||||
set_property -name "strategy" -value "Performance_RefinePlacement" -objects $obj
|
||||
set_property -name "steps.place_design.args.directive" -value "ExtraPostPlacementOpt" -objects $obj
|
||||
set_property -name "steps.phys_opt_design.args.directive" -value "Explore" -objects $obj
|
||||
set_property -name "steps.route_design.args.directive" -value "Explore" -objects $obj
|
||||
set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj
|
||||
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
|
||||
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
|
||||
|
||||
# set the current impl run
|
||||
current_run -implementation [get_runs impl_1]
|
||||
|
||||
puts "INFO: Project created:${_xil_proj_name_}"
|
||||
# Create 'drc_1' gadget (if not found)
|
||||
if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} {
|
||||
create_dashboard_gadget -name {drc_1} -type drc
|
||||
}
|
||||
set obj [get_dashboard_gadgets [ list "drc_1" ] ]
|
||||
set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
|
||||
|
||||
# Create 'methodology_1' gadget (if not found)
|
||||
if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} {
|
||||
create_dashboard_gadget -name {methodology_1} -type methodology
|
||||
}
|
||||
set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
|
||||
set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
|
||||
|
||||
# Create 'power_1' gadget (if not found)
|
||||
if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} {
|
||||
create_dashboard_gadget -name {power_1} -type power
|
||||
}
|
||||
set obj [get_dashboard_gadgets [ list "power_1" ] ]
|
||||
set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
|
||||
|
||||
# Create 'timing_1' gadget (if not found)
|
||||
if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} {
|
||||
create_dashboard_gadget -name {timing_1} -type timing
|
||||
}
|
||||
set obj [get_dashboard_gadgets [ list "timing_1" ] ]
|
||||
set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
|
||||
|
||||
# Create 'utilization_1' gadget (if not found)
|
||||
if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} {
|
||||
create_dashboard_gadget -name {utilization_1} -type utilization
|
||||
}
|
||||
set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
|
||||
set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
|
||||
set_property -name "run.step" -value "synth_design" -objects $obj
|
||||
set_property -name "run.type" -value "synthesis" -objects $obj
|
||||
|
||||
# Create 'utilization_2' gadget (if not found)
|
||||
if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} {
|
||||
create_dashboard_gadget -name {utilization_2} -type utilization
|
||||
}
|
||||
set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
|
||||
set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
|
||||
|
||||
move_dashboard_gadget -name {utilization_1} -row 0 -col 0
|
||||
move_dashboard_gadget -name {power_1} -row 1 -col 0
|
||||
move_dashboard_gadget -name {drc_1} -row 2 -col 0
|
||||
move_dashboard_gadget -name {timing_1} -row 0 -col 1
|
||||
move_dashboard_gadget -name {utilization_2} -row 1 -col 1
|
||||
move_dashboard_gadget -name {methodology_1} -row 2 -col 1
|
||||
Loading…
Add table
Add a link
Reference in a new issue