slederer/Tridora-CPU
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages 3 Wiki Activity Actions

tdraudio: add irq_enable flag, add pcmaudio library

Browse source 
runtime: disable interrupts on PTERM
stdlib: check for error state in FileSize
This commit is contained in:
slederer 2025-10-07 00:37:53 +02:00
parent 7cc9ee807d
commit 5c00dfcec9
8 changed files with 390 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

31
tridoracpu/tridoracpu.srcs/tdraudio.v
View file

@ -42,12 +42,12 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22,
assign fifo_rd_en = (div_count == 0) && channel_enable && ~fifo_empty;
assign fifo_wr_en = wr_en && (reg_sel == TDRAU_REG_AMP);
reg irq_buf, irq_done;
assign irq = irq_buf;
reg irq_buf, irq_enable;
assign irq = channel_enable && irq_buf;
reg [DATA_WIDTH-1:0] rd_data_buf;
assign rd_data = rd_data_buf;
// assign rd_data = {{DATA_WIDTH-8{1'b0}}, {4{1'b0}}, fifo_full, fifo_empty, amp_phase, channel_enable};
assign amp_val = amp_out;
assign running = channel_enable;
@ -56,7 +56,8 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22,
/* update read data buffer */
always @(posedge clk)
begin
rd_data_buf <= {{DATA_WIDTH-8{1'b0}}, {4{1'b0}}, fifo_full, fifo_empty, amp_phase, channel_enable};
rd_data_buf <= {{DATA_WIDTH-8{1'b0}},
{3{1'b0}}, irq_enable, fifo_full, fifo_empty, amp_phase, channel_enable};
end
/* irq signal to interrupt controller */
@ -65,23 +66,23 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22,
if(reset)
irq_buf <= 0;
else
if(fifo_empty && ~irq_done)
if(fifo_empty && irq_enable)
irq_buf <= 1;
else
irq_buf <= 0;
end
/* interrupt done flag, used to ensure the irq signal is set for just one clock tick */
/* interrupt enable flag */
always @(posedge clk)
begin
if(reset)
irq_done <= 0;
irq_enable <= 0;
else
if(rd_en) // reset irq done flag on any register read
irq_done <= 0;
if(ctl_reg_write)
irq_enable <= wr_data[4];
else
if(irq_buf)
irq_done <= 1;
irq_enable <= 0; // disable interrupts after an interrupt
end
/* channel enable flag */
@ -139,8 +140,8 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22,
amp_out <= AMP_BIAS;
// reset phase bit when enabling the channel
if (ctl_reg_write && wr_data[0])
// when channel is enabled, phase will be flipped on next tick
if (ctl_reg_write && wr_data[0] && ~channel_enable)
// when channel is being enabled, phase will be flipped on next tick
// because div_count will become zero
amp_phase <= 1;
end
@ -232,9 +233,6 @@ module tdraudio #(DATA_WIDTH=32) (
chan3_amp,
chan3_running, chan3_irq);
reg irq_out_buf;
assign irq_out = irq_out_buf;
reg [DAC_WIDTH:0] deltasigma_acc; // one extra bit
wire [DAC_WIDTH:0] amp_sum = chan0_amp + chan1_amp + chan2_amp + chan3_amp; // also one overflow bit here
assign gain_sel = 1; // gain select: 0 -> 12dB, 1 -> 6dB
@ -242,6 +240,9 @@ module tdraudio #(DATA_WIDTH=32) (
// assign shutdown_n = running;
assign shutdown_n = 1; /* don't enable shutdown mode, it creates a mains hum */
reg irq_out_buf;
assign irq_out = irq_out_buf;
always @(posedge clk) irq_out_buf <= chan0_irq || chan1_irq || chan2_irq || chan3_irq;
/* delta-sigma DAC */

17
tridoracpu/tridoracpu.xpr
View file

@ -378,16 +378,18 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Includes alternate algorithms for timing-driven optimization" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Similar to Performance_ExplorePostRoutePhysOpt, but enables logic optimization step (opt_design) with the ExploreWithRemap directive." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Performance_ExtraTimingOpt" Flow="Vivado Implementation 2024">
<Desc>Includes alternate algorithms for timing-driven optimization</Desc>
<StratHandle Name="Performance_ExploreWithRemap" Flow="Vivado Implementation 2024">
<Desc>Similar to Performance_ExplorePostRoutePhysOpt, but enables logic optimization step (opt_design) with the ExploreWithRemap directive.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="opt_design">
<Option Id="Directive">6</Option>
</Step>
<Step Id="power_opt_design"/>
<Step Id="place_design">
<Option Id="Directive">8</Option>
<Option Id="Directive">0</Option>
</Step>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design">
@ -395,8 +397,11 @@
</Step>
<Step Id="route_design">
<Option Id="Directive">1</Option>
<Option Id="MoreOptsStr"><![CDATA[-tns_cleanup]]></Option>
</Step>
<Step Id="post_route_phys_opt_design" EnableStepBool="1">
<Option Id="Directive">0</Option>
</Step>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream">
<Option Id="BinFile">1</Option>
</Step>