From 57430a4df69ffb7e519d2ac48915eb6eb84568a8 Mon Sep 17 00:00:00 2001 From: slederer Date: Sun, 28 Sep 2025 02:21:58 +0200 Subject: [PATCH] tdraudio: add noise generator --- tridoracpu/tridoracpu.srcs/tdraudio.v | 63 ++++++++++++++++++++++++--- tridoracpu/tridoracpu.xpr | 8 +--- 2 files changed, 59 insertions(+), 12 deletions(-) diff --git a/tridoracpu/tridoracpu.srcs/tdraudio.v b/tridoracpu/tridoracpu.srcs/tdraudio.v index ea069b0..5c19264 100644 --- a/tridoracpu/tridoracpu.srcs/tdraudio.v +++ b/tridoracpu/tridoracpu.srcs/tdraudio.v @@ -18,6 +18,19 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) ( localparam TDRAU_REG_CLK = 1; /* clock divider register */ localparam TDRAU_REG_AMP = 2; /* amplitude (volume) register */ +// localparam LFSR_WIDTH = 15; +// localparam LFSR_TAP_IDX_1 = 3; +// localparam LFSR_TAP_IDX_2 = 0; +// localparam LFSR_INIT = 'h7672; + +// localparam LFSR_WIDTH = 18; +// localparam LFSR_TAP_IDX_1 = 17; +// localparam LFSR_TAP_IDX_2 = 10; +// localparam LFSR_INIT = 'h3CBE6; + + localparam LFSR_WIDTH = 23; + localparam LFSR_INIT = 'h1; + reg channel_enable; reg [CLOCK_DIV_WIDTH-1:0] clock_div; reg [CLOCK_DIV_WIDTH-1:0] div_count; @@ -25,8 +38,12 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) ( reg [AMP_WIDTH-1:0] amp_start; reg [AMP_WIDTH-1:0] amp_out; + reg noise_enable; + reg [LFSR_WIDTH-1:0] lfsr; + wire [AMP_WIDTH-1:0] noise_out; + //assign rd_data = {{DATA_WIDTH-8-CLOCK_DIV_WIDTH{1'b0}}, div_count, {7{1'b0}}, channel_enable}; - assign rd_data = {8'b0, amp_start, {7{1'b0}}, channel_enable}; + assign rd_data = {8'b0, amp_start, {6{1'b0}}, noise_enable, channel_enable}; assign amp_val = amp_out; assign running = channel_enable; @@ -70,10 +87,38 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) ( div_count <= div_count - 1; // else just decrement it end else - if (wr_en && (reg_sel == TDRAU_REG_CLK)) - div_count <= 1; // start cycle in next clock tick + if (wr_en && (reg_sel == TDRAU_REG_CLK)) // when setting divider, + div_count <= 1; // start cycle on next clock tick end + + /* noise enable flag */ + always @(posedge clk) + begin + if(reset) + noise_enable <= 0; + else if (wr_en && (reg_sel == TDRAU_REG_CTL)) + noise_enable <= wr_data[1]; + end + + /* noise generator (Linear Feedback Shift Register) */ + always @(posedge clk) + begin + if (reset) + lfsr <= LFSR_INIT; + else + if (wr_en && (reg_sel == TDRAU_REG_CTL) && wr_data[1]) + lfsr <= LFSR_INIT; + else + if (channel_enable && noise_enable) + if (div_count == 0) + //lfsr <= { lfsr[LFSR_TAP_IDX_1] ^ lfsr[LFSR_TAP_IDX_2], lfsr[LFSR_WIDTH-1:1] }; + // shift width and tap bits taken from https://github.com/jotego/jtopl + lfsr <= { lfsr[LFSR_WIDTH-2:0], lfsr[22] ^ lfsr[9] ^ lfsr[8] ^ lfsr[0]}; + end + + assign noise_out = lfsr[0] ? amp_start : ~amp_start; + /* amplitude out */ always @(posedge clk) begin @@ -83,11 +128,17 @@ module wavegen #(DATA_WIDTH=32, CLOCK_DIV_WIDTH=22, AMP_WIDTH=16) ( amp_phase <= 1; end else - if (channel_enable && (div_count == 0)) // invert amplitude on clock tick + if (channel_enable) begin - amp_out <= amp_phase ? amp_start : ~amp_start; - amp_phase <= ~amp_phase; + if (div_count == 0) // invert amplitude on clock tick + begin + amp_out <= noise_enable ? noise_out : + amp_phase ? amp_start : ~amp_start; + amp_phase <= ~amp_phase; + end end + else + amp_out <= 0; // reset phase bit when enabling the channel if (wr_en && (reg_sel == TDRAU_REG_CTL) && wr_data[0]) diff --git a/tridoracpu/tridoracpu.xpr b/tridoracpu/tridoracpu.xpr index 1926b6c..ba7a2ef 100644 --- a/tridoracpu/tridoracpu.xpr +++ b/tridoracpu/tridoracpu.xpr @@ -358,9 +358,7 @@ - - Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, lowering multiplier threshold of inference into DSP blocks, moving shift register into BRAM, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations - + @@ -383,9 +381,7 @@ - - Default settings for Implementation. - +