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stdlib: start with valid random seed; other small changes

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-  tridoracpu: fix comment
-  add benchmark some results
This commit is contained in:
slederer 2025-03-09 01:57:11 +01:00
parent dd1e1f7b41
commit 4f504c0f48
3 changed files with 51 additions and 3 deletions
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48
examples/benchmarks.results.text Normal file
View file

@ -0,0 +1,48 @@
------------------------
Arty-A7-35T
83MHz, 64KB SRAM, 256MB DRAM
Running benchmarks.prog
empty loop 10M 00:00:09
write variable 10M 00:00:10
read variable 10M 00:00:12
integer addition 10M 00:00:16
real addition 1M 00:00:27
integer multiplication 1M 00:01:07
real multiplication 1M 00:00:58
integer division 1M 00:01:44
real division 1M 00:01:06
string indexing 1M 00:00:27
string iteration 1M 00:00:11
new/dispose 1k 1M 00:00:19
new/dispose 128k 1M 00:00:19
array copy 1k 10K 00:00:02
array copy 128k 1K 00:00:44
exp() 10K 00:00:29
cos() 10K 00:00:06
--------------------------------------
Arty-A7-35T
83MHz, 64KB SRAM, 256MB DRAM
running in DRAM only (except corelib, stdlib, runtime)
Running benchmarks.prog
empty loop 10M 00:00:30
write variable 10M 00:00:37
read variable 10M 00:00:40
integer addition 10M 00:00:48
real addition 1M 00:00:31
integer multiplication 1M 00:01:11
real multiplication 1M 00:01:03
integer division 1M 00:01:48
real division 1M 00:01:11
string indexing 1M 00:01:13
string iteration 1M 00:00:47
new/dispose 1k 1M 00:00:27
new/dispose 128k 1M 00:00:27
array copy 1k 10K 00:00:03
array copy 128k 1K 00:00:44
exp() 10K 00:00:29
cos() 10K 00:00:06

2
lib/stdlib.pas
View file

@ -151,7 +151,7 @@ var ioerrordesc: array [0..11] of string[20] = (
matherror:string[38] = 'Invalid argument to sqrt/ln/tan/cotan';
pexecerror:string[28]= 'Invalid arguments for PExec';
random_state:integer;
random_state:integer = -42;
PArgs:array [0..PArgMax] of string external;
PArgCount:integer external;

4
tridoracpu/tridoracpu.srcs/mem.v
View file

@ -28,7 +28,7 @@ module rom32 #(parameter ADDR_WIDTH = 11, DATA_WIDTH = 32)
input wire read_enable
);
wire [ADDR_WIDTH-2:0] internal_addr = addr[ADDR_WIDTH-1:2]; // -> ignore bit 0
wire [ADDR_WIDTH-2:0] internal_addr = addr[ADDR_WIDTH-1:2]; // -> ignore bits 1-0
reg [DATA_WIDTH-1:0] rom [0:(2**(ADDR_WIDTH-2))-1];
initial begin
@ -51,7 +51,7 @@ module ram32 #(parameter ADDR_WIDTH = 16, DATA_WIDTH = 32)
);
reg [DATA_WIDTH-1:0] ram [0:(2**(ADDR_WIDTH-2))-1]; // 32bit words with byte addressing
wire [ADDR_WIDTH-2:0] internal_addr = addr[ADDR_WIDTH-1:2]; // -> ignore bit 1-0
wire [ADDR_WIDTH-2:0] internal_addr = addr[ADDR_WIDTH-1:2]; // -> ignore bits 1-0
always @(posedge clk)
begin