stdlib: start with valid random seed; other small changes
- tridoracpu: fix comment - add benchmark some results
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3 changed files with 51 additions and 3 deletions
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examples/benchmarks.results.text
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48
examples/benchmarks.results.text
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@ -0,0 +1,48 @@
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------------------------
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Arty-A7-35T
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83MHz, 64KB SRAM, 256MB DRAM
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Running benchmarks.prog
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empty loop 10M 00:00:09
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write variable 10M 00:00:10
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read variable 10M 00:00:12
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integer addition 10M 00:00:16
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real addition 1M 00:00:27
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integer multiplication 1M 00:01:07
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real multiplication 1M 00:00:58
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integer division 1M 00:01:44
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real division 1M 00:01:06
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string indexing 1M 00:00:27
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string iteration 1M 00:00:11
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new/dispose 1k 1M 00:00:19
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new/dispose 128k 1M 00:00:19
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array copy 1k 10K 00:00:02
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array copy 128k 1K 00:00:44
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exp() 10K 00:00:29
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cos() 10K 00:00:06
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--------------------------------------
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Arty-A7-35T
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83MHz, 64KB SRAM, 256MB DRAM
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running in DRAM only (except corelib, stdlib, runtime)
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Running benchmarks.prog
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empty loop 10M 00:00:30
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write variable 10M 00:00:37
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read variable 10M 00:00:40
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integer addition 10M 00:00:48
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real addition 1M 00:00:31
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integer multiplication 1M 00:01:11
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real multiplication 1M 00:01:03
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integer division 1M 00:01:48
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real division 1M 00:01:11
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string indexing 1M 00:01:13
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string iteration 1M 00:00:47
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new/dispose 1k 1M 00:00:27
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new/dispose 128k 1M 00:00:27
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array copy 1k 10K 00:00:03
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array copy 128k 1K 00:00:44
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exp() 10K 00:00:29
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cos() 10K 00:00:06
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@ -151,7 +151,7 @@ var ioerrordesc: array [0..11] of string[20] = (
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matherror:string[38] = 'Invalid argument to sqrt/ln/tan/cotan';
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matherror:string[38] = 'Invalid argument to sqrt/ln/tan/cotan';
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pexecerror:string[28]= 'Invalid arguments for PExec';
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pexecerror:string[28]= 'Invalid arguments for PExec';
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random_state:integer;
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random_state:integer = -42;
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PArgs:array [0..PArgMax] of string external;
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PArgs:array [0..PArgMax] of string external;
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PArgCount:integer external;
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PArgCount:integer external;
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@ -28,7 +28,7 @@ module rom32 #(parameter ADDR_WIDTH = 11, DATA_WIDTH = 32)
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input wire read_enable
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input wire read_enable
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);
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);
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wire [ADDR_WIDTH-2:0] internal_addr = addr[ADDR_WIDTH-1:2]; // -> ignore bit 0
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wire [ADDR_WIDTH-2:0] internal_addr = addr[ADDR_WIDTH-1:2]; // -> ignore bits 1-0
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reg [DATA_WIDTH-1:0] rom [0:(2**(ADDR_WIDTH-2))-1];
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reg [DATA_WIDTH-1:0] rom [0:(2**(ADDR_WIDTH-2))-1];
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initial begin
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initial begin
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@ -51,7 +51,7 @@ module ram32 #(parameter ADDR_WIDTH = 16, DATA_WIDTH = 32)
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);
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);
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reg [DATA_WIDTH-1:0] ram [0:(2**(ADDR_WIDTH-2))-1]; // 32bit words with byte addressing
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reg [DATA_WIDTH-1:0] ram [0:(2**(ADDR_WIDTH-2))-1]; // 32bit words with byte addressing
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wire [ADDR_WIDTH-2:0] internal_addr = addr[ADDR_WIDTH-1:2]; // -> ignore bit 1-0
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wire [ADDR_WIDTH-2:0] internal_addr = addr[ADDR_WIDTH-1:2]; // -> ignore bits 1-0
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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