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LICENSE.md
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@ -4,7 +4,7 @@ All files, except where explicitly stated otherwise, are licensed according to t
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
Copyright 2024 Sebastian Lederer Copyright 2024-2026 Sebastian Lederer
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

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doc/mem.md
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@ -22,11 +22,12 @@ The _BSEL_ and _BPLC_ instructions are designed to assist with accessing bytes w
The byte ordering is big-endian. The byte ordering is big-endian.
## Accessing the I/O Area ## Accessing the I/O Area
The I/O area organizes memory slightly different. Here, pointing out individual bytes is not very useful, so the I/O controllers use register addresses with increments of one. In practice, there is only the VGA framebuffer controller which uses multiple registers. The I/O area uses the same word addressing in increments of four to access the registers of the I/O controllers. In practice, only the VGA framebuffer controller and the audio controller use multiple registers.
For the other controllers, there is a single 32 bit register that is repeated all over the address space of the corresponding I/O slot.
The individual I/O controllers each have a memory area of 128 bytes, so there is a maximum number of 16 I/O controllers. The individual I/O controllers each have a memory area of 128 bytes, so there is a maximum number of 16 I/O controllers.
Currently, only I/O slots 0-3 are being used. Currently, only I/O slots 0-4 are being used.
|I/O slot| Address | Controller | |I/O slot| Address | Controller |
|--------|---------|------------| |--------|---------|------------|

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doc/tdraudio.md
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@ -10,12 +10,12 @@ For the first channel the register addresses are:
|Address|Description| |Address|Description|
|-------|-----------| |-------|-----------|
| $A00 | Control Register | | $A00 | Control Register |
| $A01 | Clock Divider Register | | $A04 | Clock Divider Register |
| $A02 | Amplitude Register | | $A08 | Amplitude Register |
The register addresses for the second channel start at $A04, The register addresses for the second channel start at $A10,
the third channel at $A08 the third channel at $A20
and the fourth channel at $A0C. and the fourth channel at $A30.
## Reading the control register ## Reading the control register

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doc/vga.md
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@ -4,13 +4,16 @@ Registers
|Name|Address|Description| |Name|Address|Description|
|----|-------|-----------| |----|-------|-----------|
|_FB_RA_ | $900 | Read Address | |_FB_RA_ | $900 | Read Address |
|_FB_WA_ | $901 | Write Address | |_FB_WA_ | $904 | Write Address |
| _FB_IO_ | $902 | I/O Register | | _FB_IO_ | $908 | I/O Register |
| _FB_PS_ | $903 | Palette Select | | _FB_PS_ | $90C | Palette Select |
| _FB_PD_ | $904 | Palette Data | | _FB_PD_ | $910 | Palette Data |
| _FB_CTL_ | $905 | Control Register | | _FB_CTL_ | $914 | Control Register |
| _FB_SHIFTER | $918 | Shift Assist Register |
| _FB_SHIFTCOUNT | $91C | Shift Count Register |
| _FB_SHIFTERM | $920 | Shifted Mask Register |
| _FB_SHIFTERSP | $924 | Shifter Spill Register |
| _FB_MASKGEN | $928 | Mask Generator Register |
## Pixel Data ## Pixel Data
Pixel data is organized in 32-bit-words. With four bits per pixel, one word Pixel data is organized in 32-bit-words. With four bits per pixel, one word
@ -81,3 +84,54 @@ The control register contains status information. It can only be read.
The _m_ field indicates the current graphics mode. At the time of writing, it is The _m_ field indicates the current graphics mode. At the time of writing, it is
always 1 which denotes a 640x400x4 mode. always 1 which denotes a 640x400x4 mode.
The _vb_ bit is 1 when the video signal generator is in its vertical blank phase. The _vb_ bit is 1 when the video signal generator is in its vertical blank phase.
## Shift Assist Register
The *shift assist register* can be used to accelerate shifting pixel/bitmap data.
Writing a word of pixel data to this register initialises the shifting process.
After writing to the shift count register (see below), reading the shift assist
register retrieves the shifted pixel data.
Writing to the shift assist register will reset the shift count.
## Shift Count Register
Writing a number from 0-7 to the *shift count register* triggers shifting the
contents of the shift assist register. Pixel data is shifted by four bits
to the right times the shift count. Bits 31-3 of the shift count are ignored, so you can
directly write a horizontal screen coordinate to the register.
This register cannot be read.
## Shifter Mask Register
The *shifter mask register* contains the shifted pixel data converted into
a mask. See the *mask generator register* for an
explanation of the mask.
## Shifter Spill Register
The *shifter spill register* contains the pixel data that has
been shifted out to the right. For example, if the shift count is two,
the spill register contains the two rightmost pixels (bits 7-0) of
the original pixel data, placed into the two topmost pixels (bits 31-24).
The rest of the register is set to zero.
## Mask Generator Register
The *mask generator register* creates a mask from pixel data.
For each four bits of a pixel, the corresponding four mask bits
are all set to one if the pixel value is not zero.
This can be used to combine foreground and background pixel data
with a pixel value of zero for a transparent background color.
Usually, the mask will be inverted with a *NOT* instruction
to clear all pixels in the background that are set in the foreground
with an *AND* instruction
before *ORing* foreground and background together.
Example in hexadecimal, each digit is a pixel:
| Pixel Data | Mask |
|------------|------|
| $00000000 | $00000000 |
| $00000001 | $0000000F |
| $0407000F | $0F0F000F |
| $1234ABC0 | $FFFFFFF0 |