slederer/Tridora-CPU
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tridoracpu: clock, mem and top variants for CCGMA1 chip

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slederer 2025-02-27 01:41:33 +01:00
parent 91b693979d
commit 2edd5679a1
5 changed files with 419 additions and 5 deletions
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11
tridoracpu/Makefile
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@ -18,19 +18,20 @@ BITSTREAM = build/$(TOP)_00.cfg.bit
srcs = \
$(SRCDIR)/bram_tdp.v \
$(SRCDIR)/dram_bridge.v \
$(SRCDIR)/fifo.v \
$(SRCDIR)/irqctrl.v \
$(SRCDIR)/mem.v \
$(SRCDIR)/palette.v \
$(SRCDIR)/sdspi.v \
$(SRCDIR)/stackcpu.v \
$(SRCDIR)/stack.v \
$(SRCDIR)/top.v \
$(SRCDIR)/uart.v \
$(SRCDIR)/vgafb.v
#srcs += $(SRCDIR)/ccgma1_clocks.v
# for CCGMA1-EVB
srcs += $(SRCDIR)/cpuclk_ccgm.v $(SRCDIR)/top_ccgm.v $(SRCDIR)/mem_ccgm.v
# for Arty-A7
# src += $(SRCDIR)/cpuclk.v $(SRCDIR)/top.v $(SRCDIR)/mem.v
all: build synth impl
clean:
@ -49,7 +50,7 @@ $(SYNTHFILE): $(srcs)
$(YOSYS) -ql build/synth.log -p 'read -sv $(srcs); synth_gatemate -top $(TOP) -nomx8 -vlog $(SYNTHFILE)'
$(BITSTREAM): $(SYNTHFILE)
$(PNR) -v -i build/$(SYNTHFILE) -o $(TOP) $(PNRFLAGS) >build/$@.log
$(PNR) -v -i $(SYNTHFILE) -o build/$(TOP) $(PNRFLAGS) >$@.log
prog: $(BITSTREAM)
$(OFL) $(OFLFLAGS) --bitstream $(BITSTREAM)