diff --git a/tridoracpu/tridoracpu.srcs/tdraudio.v b/tridoracpu/tridoracpu.srcs/tdraudio.v index 6f41a6f..ea069b0 100644 --- a/tridoracpu/tridoracpu.srcs/tdraudio.v +++ b/tridoracpu/tridoracpu.srcs/tdraudio.v @@ -113,28 +113,45 @@ module tdraudio #(DATA_WIDTH=32) ( localparam CLOCK_DIV_WIDTH = 22; localparam AMP_WIDTH = 16; + localparam DAC_WIDTH = 18; - wire chan_sel = io_addr[6:2]; + wire [4:0] chan_sel = io_addr[6:2]; wire [1:0] reg_sel = io_addr[1:0]; wire [AMP_WIDTH-1:0] chan0_amp; wire [DATA_WIDTH-1:0] chan0_rd_data; wire chan0_running; - wire chan0_sel = chan_sel == 0; + wire chan0_sel = chan_sel == 5'd0; wire chan0_rd_en = chan0_sel && rd_en; wire chan0_wr_en = chan0_sel && wr_en; wire [AMP_WIDTH-1:0] chan1_amp; wire [DATA_WIDTH-1:0] chan1_rd_data; wire chan1_running; - wire chan1_sel = chan_sel == 1; + wire chan1_sel = chan_sel == 5'd1; wire chan1_rd_en = chan1_sel && rd_en; wire chan1_wr_en = chan1_sel && wr_en; - wire running = chan0_running || chan1_running; + wire [AMP_WIDTH-1:0] chan2_amp; + wire [DATA_WIDTH-1:0] chan2_rd_data; + wire chan2_running; + wire chan2_sel = chan_sel == 5'd2; + wire chan2_rd_en = chan2_sel && rd_en; + wire chan2_wr_en = chan2_sel && wr_en; + + wire [AMP_WIDTH-1:0] chan3_amp; + wire [DATA_WIDTH-1:0] chan3_rd_data; + wire chan3_running; + wire chan3_sel = chan_sel == 5'd3; + wire chan3_rd_en = chan3_sel && rd_en; + wire chan3_wr_en = chan3_sel && wr_en; + + wire running = chan0_running || chan1_running || chan2_running || chan3_running; assign rd_data = chan0_sel ? chan0_rd_data : chan1_sel ? chan1_rd_data : + chan2_sel ? chan2_rd_data : + chan3_sel ? chan3_rd_data : {DATA_WIDTH{1'b1}}; wavegen chan0(clk, reset, reg_sel, @@ -147,9 +164,19 @@ module tdraudio #(DATA_WIDTH=32) ( chan1_rd_en, chan1_wr_en, chan1_amp, chan1_running); - reg [AMP_WIDTH:0] deltasigma_acc; // one extra bit - wire [AMP_WIDTH:0] amp_sum = chan0_amp + chan1_amp; // also one overflow bit here - wire [AMP_WIDTH-1:0] amp_sum_scaled = amp_sum[AMP_WIDTH:1]; // shifted right to scale down + wavegen chan2(clk, reset, reg_sel, + chan2_rd_data, wr_data, + chan2_rd_en, chan2_wr_en, + chan2_amp, chan2_running); + + wavegen chan3(clk, reset, reg_sel, + chan3_rd_data, wr_data, + chan3_rd_en, chan3_wr_en, + chan3_amp, chan3_running); + + reg [DAC_WIDTH:0] deltasigma_acc; // one extra bit + wire [DAC_WIDTH:0] amp_sum = chan0_amp + chan1_amp + chan2_amp + chan3_amp; // also one overflow bit here + //wire [AMP_WIDTH-1:0] amp_sum_scaled = amp_sum[DAC_WIDTH-2:2]; // shifted right to scale down assign gain_sel = 1; // gain select: 0 -> 12dB, 1 -> 6dB assign shutdown_n = running; @@ -161,9 +188,9 @@ module tdraudio #(DATA_WIDTH=32) ( deltasigma_acc <= 0; else if (running) - deltasigma_acc <= deltasigma_acc[AMP_WIDTH-1:0] + amp_sum_scaled; + deltasigma_acc <= deltasigma_acc[DAC_WIDTH-1:0] + amp_sum; end /* 1-bit audio output */ - assign pdm_out = deltasigma_acc[AMP_WIDTH]; + assign pdm_out = deltasigma_acc[DAC_WIDTH]; endmodule diff --git a/tridoracpu/tridoracpu.xpr b/tridoracpu/tridoracpu.xpr index c5b003f..1926b6c 100644 --- a/tridoracpu/tridoracpu.xpr +++ b/tridoracpu/tridoracpu.xpr @@ -356,16 +356,14 @@ - + - + + Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, lowering multiplier threshold of inference into DSP blocks, moving shift register into BRAM, applying lower thresholds for use of carry chain in comparators and also area optimized mux optimizations + - - - - - - + + @@ -385,7 +383,9 @@ - + + Default settings for Implementation. +