vgafb: buffer maskgen outputs to avoid timing problems

lib/corelib.s

@@ -756,10 +756,9 @@ PUTPIXEL_4BPP:
 
 	; create pixel data from color value in
 	; leftmost pixel data bits (31-28)
+	LOADC 0
 	LOAD PUTPIXEL_COLOR
-	BROT
+	BPLC
-	BROT
-	BROT
 	SHL 2
 	SHL 2
 	STORE.B FB_SHIFTER	; store pixel into shifter

tridoracpu/tridoracpu.srcs/vgafb.v

@@ -162,10 +162,12 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
     reg [4:0] acc_shift_count;
     reg acc_start_shift;
     reg [VMEM_DATA_WIDTH-1:0] acc_mask_in;
-    wire [VMEM_DATA_WIDTH-1:0] acc_mask_out;
+    reg [VMEM_DATA_WIDTH-1:0] acc_mask_buf;
-    wire [VMEM_DATA_WIDTH-1:0] acc_shifter_mask;
+    reg [VMEM_DATA_WIDTH-1:0] acc_shiftmask_buf;
+    wire [VMEM_DATA_WIDTH-1:0] acc_shifter_mask = acc_shiftmask_buf;
     wire [VMEM_DATA_WIDTH-1:0] acc_shifter_out_h = acc_shifter_out[(VMEM_DATA_WIDTH*2)-1:VMEM_DATA_WIDTH];
     wire [VMEM_DATA_WIDTH-1:0] acc_shifter_out_l = acc_shifter_out[VMEM_DATA_WIDTH-1:0];
+
  `endif
 
     assign vmem_rd_en = rd_en;
@@ -176,9 +178,9 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
                      (reg_sel == REG_CTL)       ? status :
 `ifdef ENABLE_FB_ACCEL
                      (reg_sel == REG_SHIFTER)   ? acc_shifter_out_h:
-                     (reg_sel == REG_SHIFTERM)  ? acc_shifter_mask :
+                     (reg_sel == REG_SHIFTERM)  ? acc_shiftmask_buf :
                      (reg_sel == REG_SHIFTERSP) ? acc_shifter_out_l :
-                     (reg_sel == REG_MASKGEN)   ? acc_mask_out :
+                     (reg_sel == REG_MASKGEN)   ? acc_mask_buf :
  `endif
                      32'hFFFFFFFF;
 
@@ -335,27 +337,34 @@ module vgafb #(VMEM_ADDR_WIDTH = 15, VMEM_DATA_WIDTH = 32) (
             acc_mask_in <= wr_data;
     end
 
-    assign acc_mask_out = {
+    // mask output is buffered to avoid timing problems
-        {4{|{acc_mask_in[31:28]}}},
+    always @(posedge cpu_clk)
-        {4{|{acc_mask_in[27:24]}}},
+    begin
-        {4{|{acc_mask_in[23:20]}}},
+        acc_mask_buf <= {
-        {4{|{acc_mask_in[19:16]}}},
+            {4{~|{acc_mask_in[31:28]}}},
-        {4{|{acc_mask_in[15:12]}}},
+            {4{~|{acc_mask_in[27:24]}}},
-        {4{|{acc_mask_in[11:8]}}},
+            {4{~|{acc_mask_in[23:20]}}},
-        {4{|{acc_mask_in[7:4]}}},
+            {4{~|{acc_mask_in[19:16]}}},
-        {4{|{acc_mask_in[3:0]}}}
+            {4{~|{acc_mask_in[15:12]}}},
-    };
+            {4{~|{acc_mask_in[11:8]}}},
+            {4{~|{acc_mask_in[7:4]}}},
+            {4{~|{acc_mask_in[3:0]}}}
+        };
+    end
 
-    assign acc_shifter_mask = {
+    always @(posedge cpu_clk)
-        {4{|{acc_shifter_out_h[31:28]}}},
+    begin
-        {4{|{acc_shifter_out_h[27:24]}}},
+        acc_shiftmask_buf = {
-        {4{|{acc_shifter_out_h[23:20]}}},
+            {4{~|{acc_shifter_out_h[31:28]}}},
-        {4{|{acc_shifter_out_h[19:16]}}},
+            {4{~|{acc_shifter_out_h[27:24]}}},
-        {4{|{acc_shifter_out_h[15:12]}}},
+            {4{~|{acc_shifter_out_h[23:20]}}},
-        {4{|{acc_shifter_out_h[11:8]}}},
+            {4{~|{acc_shifter_out_h[19:16]}}},
-        {4{|{acc_shifter_out_h[7:4]}}},
+            {4{~|{acc_shifter_out_h[15:12]}}},
-        {4{|{acc_shifter_out_h[3:0]}}}
+            {4{~|{acc_shifter_out_h[11:8]}}},
-    };
+            {4{~|{acc_shifter_out_h[7:4]}}},
+            {4{~|{acc_shifter_out_h[3:0]}}}
+        };
+    end
 `endif
 
     //

tridoracpu/tridoracpu.xpr

@@ -358,9 +358,7 @@
   <Runs Version="1" Minor="22">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Performs optimizations which creates alternative logic technology mapping, including disabling LUT combining, forcing F7/F8/F9 to logic, increasing the threshold of shift register inference." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Flow_AlternateRoutability" Flow="Vivado Synthesis 2024">
+        <StratHandle Name="Flow_AlternateRoutability" Flow="Vivado Synthesis 2024"/>
-          <Desc>Performs optimizations which creates alternative logic technology mapping, including disabling LUT combining, forcing F7/F8/F9 to logic, increasing the threshold of shift register inference.</Desc>
-        </StratHandle>
         <Step Id="synth_design">
           <Option Id="Directive">3</Option>
           <Option Id="NoCombineLuts">1</Option>
@@ -384,9 +382,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Best predicted directive for place_design." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Performance_Auto_1" Flow="Vivado Implementation 2024">
+        <StratHandle Name="Performance_Auto_1" Flow="Vivado Implementation 2024"/>
-          <Desc>Best predicted directive for place_design.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design">
           <Option Id="Directive">0</Option>