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vgafb: buffer maskgen outputs to avoid timing problems

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slederer 2026-01-31 17:24:36 +01:00
parent 8900eb90be
commit 1e56251fc1
3 changed files with 37 additions and 33 deletions
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8
tridoracpu/tridoracpu.xpr
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@ -358,9 +358,7 @@
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Performs optimizations which creates alternative logic technology mapping, including disabling LUT combining, forcing F7/F8/F9 to logic, increasing the threshold of shift register inference." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Flow_AlternateRoutability" Flow="Vivado Synthesis 2024">
<Desc>Performs optimizations which creates alternative logic technology mapping, including disabling LUT combining, forcing F7/F8/F9 to logic, increasing the threshold of shift register inference.</Desc>
</StratHandle>
<StratHandle Name="Flow_AlternateRoutability" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design">
<Option Id="Directive">3</Option>
<Option Id="NoCombineLuts">1</Option>
@ -384,9 +382,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Best predicted directive for place_design." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Performance_Auto_1" Flow="Vivado Implementation 2024">
<Desc>Best predicted directive for place_design.</Desc>
</StratHandle>
<StratHandle Name="Performance_Auto_1" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design">
<Option Id="Directive">0</Option>