Update READMEs

README.md

@@ -1,5 +1,5 @@
-# Tridora System
-Tridora is a homebrew CPU written in Verilog and a matching software environment,
+# Tridora-CPU
+The Tridora-CPU is a homebrew CPU written in Verilog and a matching software environment,
 including a Pascal compiler and assembler.
 Everything was created from the ground up (except soldering stuff).
 Everything is as simple as possible while still being reasonably useful.
@@ -8,7 +8,7 @@ Everything is open source, so you can read, understand and modify the whole syst
 ## Overview
 - homebrew CPU written in Verilog implemented on an FPGA
 - 32-bit word-oriented stack machine architecture
-- running at 83 MHz on an Arty-A7 board with four clocks per instruction
+- running at 77 MHz on an Arty-A7 board with four clocks per instruction
 - has its own instruction set architecture, compatible with nothing
 - additional IO controllers on FPGA: UART (serial console), SD-Card, VGA
 - Pascal compiler written from zero
@@ -30,13 +30,40 @@ has a strange mixture of features from three different eras of computing:
 - speed is like a fast 16-bit CPU, also 16-bit instruction words
 - 32-bit word size from the 32-bit era
 
+It might remind you of the UCSD-P-System and early Turbo-Pascal versions.
+
+Other inspirations were, among others, in no particular order:
+
+- the Novix 4016 CPU (a stack machine CPU designed for Forth, mainly by Charles Moore)
+- the J1 CPU by James Bowman (which is not entirely unlike the Novix 4016)
+- the Lilith computer by Niklaus Wirth and his team (a stack CPU designed for Modula-2)
+- the PERQ workstation (also a stack CPU designed for Pascal)
+- the Magic-1 by Bill Buzbee
+- the OPC by revaldinho
+
+## April 2025 Update
+The clock has been reduced to 77 MHz from 83 MHz. Apparently the design was at the limit and
+timing problems were cropping up seemingly at random. Reducing the clock speed made some
+enhancements and bugfixes possible. Also, the project files work with Vivado 2024 now.
+
+Most importantly, the Tridora-CPU now has an instruction cache with a size of 16 bytes or eight instructions.
+This increases execution speed when running code out of DRAM (that is, above 64KB). In a simple
+benchmark program, the CPU is about twice as fast.
+Many programs fit into the lower 64KB of RAM, which can be accessed without latency, and will
+have no noticable speed increase.
+
+There have also been a number of bug fixes for the compiler and some for the assembler. This makes
+compiling even larger and more complex programs possible. An example of this is ECL-Rogue, a variant of Rogue written
+Pascal, which has been ported to Tridora-Pascal and is now included
+on the emulator image.
+
 ## Links/Downloads
 - the [source repository](https://gitlab.com/slederer/Tridora-CPU)
 - the [Hackaday project](https://hackaday.io/project/198324-tridora-cpu) (mostly copy-paste from this README)
 - the [YouTube channel](https://www.youtube.com/@tridoracpu/videos) with some demo videos
-- the [emulator](https://git.insignificance.de/slederer/-/packages/generic/tridoraemu/0.0.4/files/11) (source and windows binary)
-- the [FPGA bitstream](https://git.insignificance.de/slederer/-/packages/generic/tdr-bitstream/0.0.1/files/3) for the Arty-A7-35T board
-- an [SD-card image](https://git.insignificance.de/slederer/-/packages/generic/tdr-cardimage/0.0.3/files/9)
+- the [emulator](https://git.insignificance.de/slederer/-/packages/generic/tridoraemu/0.0.5/files/12) (source and windows binary)
+- the [FPGA bitstream](https://git.insignificance.de/slederer/-/packages/generic/tdr-bitstream/0.0.2/files/14) for the Arty-A7-35T board
+- an [SD-card image](https://git.insignificance.de/slederer/-/packages/generic/tdr-cardimage/0.0.4/files/13)
 
 Contact the author here: tridoracpu [at] insignificance.de
 
@@ -67,7 +94,7 @@ Two Pmods are used for a complete system:
 As the Arty-A7-35T is no longer in production, it should be easy to
 use the Arty-A7-100T instead, but this has not been tested yet.
 
-Other boards under consideration are the Digilent Nexys-A7 and the Olimex GateMateA1-EVB.
+Other boards under consideration are the Digilent Nexys-A7 and the Arty-S7.
 
 ## Pascal Language
 - Wirth Pascal
@@ -76,7 +103,7 @@ Other boards under consideration are the Digilent Nexys-A7 and the Olimex GateMa
 - safe strings (runtime information about max/current size)
 - tiny sets (machine word sized), that means no SET OF CHAR
 - array literals with IN-operator, which can replace most uses of SET OF CHAR
-- nested procedures with some limitations
+- nested procedures
 - 32 bit software floating point with low precision (5-6 digits)
 - break and exit statements, no continue yet
 - static variable initialization for global variables
@@ -107,7 +134,7 @@ Other boards under consideration are the Digilent Nexys-A7 and the Olimex GateMa
 - for **rom.mem** and **rommon.prog**, find both files in the **lib** directory after running **make nativeprogs** (or **make.bat**) in the **pcomp** directory (see above)
 
 ## Building the FPGA bitstream
-- install Vivado (known to work with 2020.1, known NOT to work with 2024.1)
+- install Vivado (April-2025-Update tested with 2024.2)
 - install the package for your board in Vivado (Tools -> Vivado Store -> Boards)
 - copy the ROM image (**rom.mem**) into the **tridoracpu** directory (see above)
 - start Vivado and open the project file **tridoracpu.xpr** in the **tridoracpu** directory
@@ -128,3 +155,8 @@ See the emulator [README](tridoraemu/README.md).
 - [The Mostly Missing Pascal Programming Guide](doc/pascalprogramming.md)
 
 More documentation is coming, as time permits.
+
+## Credits
+The Tridora-CPU uses the UART from the J1 CPU by James Bowman (*uart.v*), see https://github.com/jamesbowman/j1
+
+The VGA framebuffer uses code from Project F by Will Green, see https://projectf.io